Matteo Sonza Reorda
Orcid: 0000-0003-2899-7669Affiliations:
- Polytechnic University of Turin, Italy
According to our database1,
Matteo Sonza Reorda
authored at least 503 papers
between 1988 and 2023.
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Bibliography
2023
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Computers, May, 2023
Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques.
Microprocess. Microsystems, April, 2023
A Toolchain to Quantify Burn-In Stress Effectiveness on Large Automotive System-on-Chips.
IEEE Access, 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Analyzing the Impact of Different Real Number Formats on the Structural Reliability of TCUs in GPUs.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters.
Proceedings of the High Performance Computing, 2023
Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units.
Proceedings of the International Conference for High Performance Computing, 2023
RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 32nd IEEE International Symposium on Industrial Electronics, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.
Proceedings of the IEEE European Test Symposium, 2023
Targeting different defect-oriented fault models in IC testing: an experimental approach.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Evaluating low-level software-based hardening techniques for configurable GPU architectures.
J. Supercomput., 2022
A New Method to Generate Software Test Libraries for In-Field GPU Testing Resorting to High-Level Languages.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
A novel Pattern Selection Algorithm to reduce the Test Cost of large Automotive Systems-on-Chip.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip.
Proceedings of the IEEE International Test Conference, 2022
A Multi-level Approach to Evaluate the Impact of GPU Permanent Faults on CNN's Reliability.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference in Asia, 2022
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022
Reliability Assessment of Neural Networks in GPUs: A Framework For Permanent Faults Injections.
Proceedings of the 31st IEEE International Symposium on Industrial Electronics, 2022
Effective fault simulation of GPU's permanent faults for reliability estimation of CNNs.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
A comparative overview of ATPG flows targeting traditional and cell-aware fault models.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Neural Network's Reliability to Permanent Faults: Analyzing the Impact of Performance Optimizations in GPUs.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries.
Proceedings of the IEEE European Test Symposium, 2022
An Optimized Burn-In Stress Flow targeting Interconnections logic to Embedded Memories in Automotive Systems-on-Chip.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization.
Proceedings of the IEEE European Test Symposium, 2022
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
Online scheduling of concurrent Memory BISTs execution at Real-Time Operating-System level.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
J. Supercomput., 2021
Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks.
IEEE Access, 2021
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Combining Architectural Simulation and Software Fault Injection for a Fast and Accurate CNNs Reliability Evaluation on GPUs.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Protecting GPU's Microarchitectural Vulnerabilities via Effective Selective Hardening.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Revealing GPUs Vulnerabilities by Combining Register-Transfer and Software-Level Fault Injection.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 30th IEEE Asian Test Symposium, 2021
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor.
Proceedings of the 30th IEEE Asian Test Symposium, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks.
IEEE Trans. Computers, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs.
Proceedings of the IEEE European Test Symposium, 2020
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
Applicative System Level Test introduction to Increase Confidence on Screening Quality.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
2019
An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests.
J. Circuits Syst. Comput., 2019
Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications.
IEEE Access, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks.
Proceedings of the IEEE International Test Conference in Asia, 2018
Towards an automatic approach for hardware verification according to ISO 26262 functional safety standard.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
RESCUE: Cross-Sectoral PhD Training Concept for Interdependent Reliability, Security and Quality.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers, 2017
IEEE Trans. Computers, 2017
J. Circuits Syst. Comput., 2017
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits.
J. Electron. Test., 2017
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms.
J. Electron. Test., 2017
An automatic approach to perform the verification of hardware designs according to the ISO26262 functional safety standard.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation.
Microprocess. Microsystems, 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
J. Electron. Test., 2016
J. Electron. Test., 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables.
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs.
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test.
IEEE Trans. Computers, 2014
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectron. Reliab., 2014
Selected Peer-Reviewed Articles from the 14th IEEE Latin-American Test Workshop, Cordoba, Argentina, April 3-5, 2013.
J. Low Power Electron., 2014
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test.
J. Electron. Test., 2014
J. Electron. Test., 2014
Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players?
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques.
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 9th International Design and Test Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
On the in-field test of Branch Prediction Units using the correlated predictor mechanism.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
An effective approach to automatic functional processor test generation for small-delay faults.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Hardening of serial communication protocols for potentially critical systems in automotive applications: LIN bus.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors.
Proceedings of the 8th International Design and Test Symposium, 2013
On the on-line functional test of the Reorder Buffer memory in superscalar processors.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
On the use of embedded debug features for permanent and transient fault resilience in microprocessors.
Microprocess. Microsystems, 2012
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
On the optimized generation of Software-Based Self-Test programs for VLIW processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
IEEE Trans. Ind. Electron., 2011
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test.
J. Electron. Test., 2011
On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Functional test generation for the pLRU replacement mechanism of embedded cache memories.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 16th European Test Symposium, 2011
An FPGA-Emulation-Based Platform for Characterization of Digital Baseband Communication Systems.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Dependable Secur. Comput., 2010
Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.
IET Comput. Digit. Tech., 2010
Generating power-hungry test programs for power-aware validation of pipelined processors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
A novel scalable and reconfigurable emulation platform for embedded systems verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Analysis of root causes of alpha sensitivity variations on microprocessors manufactured using different cell layouts.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010
A hardware accelerated framework for the generation of design validation programs for SMT processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Test Program Generation for Communication Peripherals in Processor-Based SoC Devices.
IEEE Des. Test Comput., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Exploiting embedded FPGA in on-line software-based test strategies for microprocessor cores.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
An efficient fault simulation technique for transition faults in non-scan sequential circuits.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electron. Test., 2008
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
Proceedings of the Applications of Evolutionary Computing, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electron. Test., 2007
A software-based methodology for the generation of peripheral test sets based on high-level descriptions.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
IEEE Trans. Computers, 2006
Int. J. Parallel Program., 2006
IEEE Des. Test Comput., 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Software-Based On-Line Test of Communication Peripherals in Processor-Based Systems for Automotive Applications.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
A New Approach to Cope with Single Event Upsets in Processor-based Systems.
Proceedings of the 7th Latin American Test Workshop, 2006
A Fault Injection Environment for SoPC's Embedded Microprocessors.
Proceedings of the 7th Latin American Test Workshop, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Springer, ISBN: 978-0-387-26060-0, 2006
2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
New evolutionary techniques for test-program generation for complex microprocessor cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005
Proceedings of the Applications of Evolutionary Computing, 2005
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 10th European Test Symposium, 2005
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
2004
J. Electron. Test., 2004
J. Electron. Test., 2004
A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
J. Electron. Test., 2004
A multi-level approach to the dependability analysis of networked systems based on the CAN protocol.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Evaluating the Effects of Transient Faults on Vehicle Dynamic Performance in Automotive Systems.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA.
Proceedings of the 2004 Design, 2004
2003
Microelectron. J., 2003
J. Electron. Test., 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy?
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Proceedings of the 8th European Test Workshop, 2003
An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories.
Proceedings of the 2003 Design, 2003
2002
ACM Trans. Design Autom. Electr. Syst., 2002
An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits.
J. Electron. Test., 2002
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and Drawbacks.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
An Overview Covering the Different Solutions: from radiation testing to Software Fault Injection.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the Applications of Evolutionary Computing, 2002
Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Congress on Evolutionary Computation, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 1st IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2001), 2001
Proceedings of the 2001 ACM Symposium on Applied Computing (SAC), 2001
Effectiveness and Limitations of Various Software Techniques for "Soft Error" Detection: A Comparative Study.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of the Applications of Evolutionary Computing, 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
System safety through automatic high-level code transformations: an experimental evaluation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the Computer Safety, 2000
Proceedings of the Integrated Circuit Design, 2000
Hardening the Software with Respect to Transient Errors: a Method and Experimental Results.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures.
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000
A genetic algorithm-based system for generating test programs for microprocessor IP cores.
Proceedings of the 12th IEEE International Conference on Tools with Artificial Intelligence (ICTAI 2000), 2000
Proceedings of the Evolvable Systems: From Biology to Hardware, 2000
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Proceedings of the Real-World Applications of Evolutionary Computing, 2000
Proceedings of the Real-World Applications of Evolutionary Computing, 2000
Proceedings of the 5th European Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000
An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 2000 Design, 2000
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience.
Proceedings of the 2000 Design, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Proceedings of the 2000 Congress on Evolutionary Computation, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
J. Univers. Comput. Sci., 1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the Computer Safety, 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Approximate Equivalence Verification for Protocol Interface Implementation via Genetic Algorithms.
Proceedings of the Evolutionary Image Analysis, 1999
Proceedings of the Evolutionary Image Analysis, 1999
Proceedings of the 4th European Test Workshop, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 1999 Design, 1999
Proceedings of the 1999 Congress on Evolutionary Computation, 1999
Proceedings of the 1999 Congress on Evolutionary Computation, 1999
1998
ACM Trans. Design Autom. Electr. Syst., 1998
Formal Methods Syst. Des., 1998
IEEE Des. Test Comput., 1998
The training environment for the course on microprocessor systems at the Politecnico di Torino.
Proceedings of the 1998 workshop on Computer architecture education, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
Proceedings of the 1998 ACM symposium on Applied Computing, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 1998 Design, 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
SAARA: a simulated annealing algorithm for test pattern generation for digital circuits.
Proceedings of the 1997 ACM symposium on Applied Computing, 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the High-Performance Computing and Networking, 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the European Design and Test Conference, 1997
A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs.
Proceedings of the European Design and Test Conference, 1997
Simulation-based verification of network protocols performance.
Proceedings of the Advances in Hardware Design and Verification, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996
Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits.
Proceedings of the Parallel Problem Solving from Nature, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996
Proceedings of the Eigth International Conference on Tools with Artificial Intelligence, 1996
A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture.
Proceedings of the High-Performance Computing and Networking, 1996
Proceedings of the High-Performance Computing and Networking, 1996
A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits.
Proceedings of the High-Performance Computing and Networking, 1996
Proceedings of the conference on European design automation, 1996
Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment.
Proceedings of the conference on European design automation, 1996
On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications.
Proceedings of the Dependable Computing, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case Study.
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
Exploiting massively parallel architectures for the solution of diffusion and propagation problems.
Proceedings of the High-Performance Computing and Networking, 1995
Proceedings of the High-Performance Computing and Networking, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
Proceedings of the 1995 European Design and Test Conference, 1995
1994
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994
An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits.
Proceedings of the Sixth International Conference on Tools with Artificial Intelligence, 1994
Proceedings of the First IEEE Conference on Evolutionary Computation, 1994
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994
An experimental analysis of the effectiveness of the circular self-test path technique.
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
J. Electron. Test., 1993
Proceedings of the 1993 Euromicro Workshop on Parallel and Distributed Processing, 1993
1992
A simulation-based approach to test pattern generation for synchronous sequential circuits.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
1990
Microprocessing and Microprogramming, 1990
Microprocessing and Microprogramming, 1990
J. Electron. Test., 1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the Computer-Aided Verification, 1990
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990
1989
Expressing logical and temporal conditions in simulation environments: TPDL<sup>*</sup>.
Microprocessing and Microprogramming, 1989
1988
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988