Debjyoti Ghosh

Orcid: 0000-0002-2233-0575

According to our database1, Debjyoti Ghosh authored at least 14 papers between 2003 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Commanding and Re-Dictation: Developing Eyes-Free Voice-Based Interaction for Editing Dictated Text.
ACM Trans. Comput. Hum. Interact., 2020

Practical Empathy: The Duality of Social and Transactional Roles of Conversational Agents in Giving Health Advice.
Proceedings of the 41st International Conference on Information Systems, 2020

EYEditor: Towards On-the-Go Heads-Up Text Editing Using Voice and Manual Input.
Proceedings of the CHI '20: CHI Conference on Human Factors in Computing Systems, 2020

2018
EDITalk: Towards Designing Eyes-free Interactions for Mobile Word Processing.
Proceedings of the 2018 CHI Conference on Human Factors in Computing Systems, 2018

Teach Me Fast: How to Optimize Online Lecture Video Speeding for Learning in Less Time?
Proceedings of the Sixth International Symposium of Chinese CHI, 2018

Assessing the Utility of the System Usability Scale for Evaluating Voice-based User Interfaces.
Proceedings of the Sixth International Symposium of Chinese CHI, 2018

2015
JUPred_SVM: Prediction of Phosphorylation Sites Using a Consensus of SVM Classifiers.
Proceedings of Fifth International Conference on Soft Computing for Problem Solving, 2015

JUPred_MLP: Prediction of Phosphorylation Sites Using a Consensus of MLP Classifiers.
Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications, 2015

2005
Low-power scan design using first-level supply gating.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points.
Proceedings of the 10th European Test Symposium, 2005

2004
A Technique to Reduce Power and Test Application Time in BIST.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A Novel Low-Power Scan Design Technique Using Supply Gating.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003


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