Doowon Lee

Orcid: 0000-0003-0046-7746

According to our database1, Doowon Lee authored at least 15 papers between 2009 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Bypassing Multicore Memory Bugs With Coarse-Grained Reconfigurable Logic.
IEEE Trans. Computers, 2022

IZO/ITO Double-Layered Transparent Conductive Oxide for Silicon Heterojunction Solar Cells.
IEEE Access, 2022

Improved Electrical and Optical Properties of IGZO Transparent Conductive Oxide Due to Microwave Treatment: Application to Silicon Solar Cells.
IEEE Access, 2022

Improved Resistive Switching Observed in Ti/Zr<sub>3</sub>N<sub>2</sub>/p-Si Capacitor via Hydrogen Passivation.
IEEE Access, 2022

2021
Self-Rectifying Characteristics Observed in O-Doped ZrN Resistive Switching Memory Devices Using Schottky Barrier Type Bottom Electrode.
IEEE Access, 2021

2018
Decompose and Conquer: Addressing Evasive Errors in Systems on Chip.
PhD thesis, 2018

Low-Overhead Microarchitectural Patching for Multicore Memory Subsystems.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation.
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

AGARSoC: Automated test and coverage-model generation for verification of accelerator-rich SoCs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Probabilistic bug-masking analysis for post-silicon tests in microprocessor verification.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Highly Fault-tolerant NoC Routing with Application-aware Congestion Management.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

NoCVision: A Network-on-Chip Dynamic Visualization Solution.
Proceedings of the 8th International Workshop on Network on Chip Architectures, 2015

2014
Brisk and limited-impact NoC routing reconfiguration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2009
VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009


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