Dustin Dunwell

According to our database1, Dustin Dunwell authored at least 10 papers between 2006 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2014
A passive resonant clocking network for distribution of a 2.5-GHz clock in a flash ADC.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Modeling Oscillator Injection Locking Using the Phase Domain Response.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Channel characterization using jitter measurements.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2010
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2007
Computer design of super-orthogonal space-time trellis codes.
IEEE Trans. Wirel. Commun., 2007

2006
24 GHz Low-Noise Amplifiers using High Q Series-Stub Transmission Lines in 0.18µm CMOS.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006


  Loading...