According to our database1, David Cassan authored at least 5 papers between 2011 and 2021.
Legend:Book In proceedings Article PhD thesis Other
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Performance of edge tap decision feedback equalization methods for wireline receivers.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the 38th European Solid-State Circuit conference, 2012
An 8.4mW/Gb/s 4-lane 48Gb/s multi-standard-compliant transceiver in 40nm digital CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011