According to our database1, Ryan Bespalko authored at least 3 papers between 2006 and 2019.
Legend:Book In proceedings Article PhD thesis Other
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Performance of edge tap decision feedback equalization methods for wireline receivers.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Analysis and Design of a 10 Gbps Transimpedance Amplifier using 0.18µm CMOS technology.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006