James Bailey

According to our database, James Bailey authored at least 4 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver.

James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto

IEEE J. Solid State Circuits, 2022

2021

A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s.

Behraz Vatankhahghadim, Nijwm Wary, James Bailey, Anthony Chan Carusone

IEEE Open J. Circuits Syst., 2021

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver.

James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.

Shayan Shahramian, Behzad Dehlaghi, Joshua Liang, Ryan Bespalko, Dustin Dunwell, James Bailey, Bo Wang, Alireza Sharif Bakhtiar, Michael O'Farrell, Kerry Tang, Anthony Chan Carusone, David Cassan, Davide Tonietto

Proceedings of the IEEE International Solid- State Circuits Conference, 2019