Shayan Shahramian

According to our database1, Shayan Shahramian authored at least 10 papers between 2011 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
A 1.41pJ/b 56Gb/s PAM-4 Wireline Receiver Employing Enhanced Pattern Utilization CDR and Genetic Adaptation Algorithms in 7nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016
Edge-Based Adaptation for a 1 IIR + 1 Discrete-Time Tap DFE Converging in 5~µs.
IEEE J. Solid State Circuits, 2016

23.7 A 16Gb/s 1 IIR + 1 DT DFE compensating 28dB loss with edge-based adaptation converging in 5µs.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Correction to "A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS".
IEEE J. Solid State Circuits, 2015

A 0.41 pJ/Bit 10 Gb/s Hybrid 2 IIR and 1 Discrete-Time DFE Tap in 28 nm-LP CMOS.
IEEE J. Solid State Circuits, 2015

2014
A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS.
Proceedings of the ESSCIRC 2014, 2014

2012
Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011
A pattern-guided adaptive equalizer in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011


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