Eberle A. Rambo

Orcid: 0000-0002-4264-9436

According to our database1, Eberle A. Rambo authored at least 16 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2022
The Self-Aware Information Processing Factory Paradigm for Mixed-Critical Multiprocessing.
IEEE Trans. Emerg. Top. Comput., 2022

2020
Bridging the Gap between Resilient Networks-on-Chip and Real-Time Systems.
IEEE Trans. Emerg. Top. Comput., 2020

2019
Fault-Tolerant Many-Cores for Mixed-Critical Real-Time Systems.
PhD thesis, 2019

Providing Integrity in Real-Time Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2019

The Information Processing Factory: Organization, Terminology, and Definitions.
CoRR, 2019

The information processing factory: a paradigm for life cycle management of dependable systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2017
Power and area evaluation of a fault-tolerant network-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Designing Networks-on-Chip for High Assurance Real-Time Systems.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

Replica-Aware Co-Scheduling for Mixed-Criticality.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

2016
Providing formal latency guarantees for ARQ-based protocols in Networks-on-Chip.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Worst-case communication time analysis of networks-on-chip with shared virtual channels.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
FMEA-based analysis of a Network-on-Chip for mixed-critical systems.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

Failure analysis of a network-on-chip for real-time mixed-critical systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
On-the-fly verification of memory consistency with concurrent relaxed scoreboards.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
On ESL verification of memory consistency for system-on-chip multiprocessing.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Automatic generation of memory consistency tests for chip multiprocessing.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011


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