Elmet Orasson

According to our database1, Elmet Orasson authored at least 9 papers between 2001 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A tool set for teaching design-for-testability of digital circuits.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

2015
Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs.
Proceedings of the VLSI-SoC: Design for Reliability, Security, and Low Power, 2015

Scalable algorithm for structural fault collapsing in digital circuits.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Double Phase Fault Collapsing with Linear Complexity in Digital Circuits.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2012
Functional Built-In Self-Test for processor cores in SoC.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2008
Hybrid BIST optimization using reseeding and test set compaction.
Microprocess. Microsystems, 2008

2007
Learning Digital Test and Diagnostics via Internet.
Int. J. Online Eng., 2007

Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems.
Proceedings of the IEEE Second International Symposium on Industrial Embedded Systems, 2007

2001
Fast Test Cost Calculation for Hybrid BIST in Digital Systems.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001


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