Eshan Singh

According to our database, Eshan Singh authored at least 14 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

LFPS: Learned Formal Proof Strengthening for Efficient Hardware Verification.

Minwoo Kang, Azade Nova, Eshan Singh, Geetheeka Sharron Bathini, Yuriy Viktorov

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2021

Effective Pre-Silicon Verification of Processor Cores by Breaking the Bounds of Symbolic Quick Error Detection.

Karthik Ganesan, Florian Lonsing, Srinivasa Shashank Nuthakki, Eshan Singh, Mohammad Rahmani Fadiheh, Wolfgang Kunz, Dominik Stoffel, Clark W. Barrett, Subhasish Mitra

CoRR, 2021

2020

Gap-free Processor Verification by S²QED and Property Generation.

Keerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A-QED Verification of Hardware Accelerators.

Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Unlocking the Power of Formal Hardware Verification with CoSA and Symbolic QED: Invited Paper.

Florian Lonsing, Karthik Ganesan, Makai Mann, Srinivasa Shashank Nuthakki, Eshan Singh, Mario Srouji, Yahan Yang, Subhasish Mitra, Clark W. Barrett

Proceedings of the International Conference on Computer-Aided Design, 2019

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.

Eshan Singh, Keerthikumara Devarajegowda, Sebastian Simon, Ralf Schnieder, Karthik Ganesan, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz, Clark W. Barrett, Wolfgang Ecker, Subhasish Mitra

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2017

Logic Bug Detection and Localization Using Symbolic Quick Error Detection.

Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra

CoRR, 2017

E-QED: Electrical Bug Localization During Post-silicon Validation Enabled by Quick Error Detection and Formal Methods.

Eshan Singh, Clark W. Barrett, Subhasish Mitra

Proceedings of the Computer Aided Verification - 29th International Conference, 2017

2016

Symbolic Quick Error Detection for Pre-Silicon and Post-Silicon Validation: Frequently Asked Questions.

Eshan Singh, David Lin, Clark W. Barrett, Subhasish Mitra

IEEE Des. Test, 2016

2015

A structured approach to post-silicon validation and debug using symbolic quick error detection.

David Lin, Eshan Singh, Clark W. Barrett, Subhasish Mitra

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

Modeling location based wafer die yield variation in estimating 3D stacked IC yield from wafer to wafer stacking.

Eshan Singh

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect Clustering.

Eshan Singh

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2012

Impact of Radial defect clustering on 3D stacked IC yield from wafer to wafer stacking.

Eshan Singh

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Exploiting rotational symmetries for improved stacked yields in W2W 3D-SICs.

Eshan Singh

Proceedings of the 29th IEEE VLSI Test Symposium, 2011