Peng Wei

Orcid: 0000-0002-4034-4540

Affiliations:

University of California at Los Angeles, Center for Domain-Specific Computing, CA, USA

According to our database¹, Peng Wei authored at least 21 papers between 2015 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

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PhD thesis

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Bibliography

2021

MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.

[BibT_eX]

[DOI]

Saranyu Chattopadhyay

Proceedings of the Formal Methods in Computer Aided Design, 2021

2020

A-QED Verification of Hardware Accelerators.

[BibT_eX]

[DOI]

Eshan Singh

Florian Lonsing

Saranyu Chattopadhyay

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2019

Customizable Computing - From Single Chip to Datacenters.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Enabling Customized Computing in Datacenters: from Accelerator Design to System Integration.

[BibT_eX]

[DOI]

Peng Wei

PhD thesis, 2018

AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture.

[BibT_eX]

[DOI]

CoRR, 2018

Best-Effort FPGA Programming: A Few Steps Can Go a Long Way.

[BibT_eX]

[DOI]

CoRR, 2018

SODA: stencil with optimized dataflow architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining.

[BibT_eX]

[DOI]

Jason Cong

Peng Wei

Cody Hao Yu

Proceedings of the 10th USENIX Workshop on Hot Topics in Cloud Computing, 2018

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Latte: Locality Aware Transformation for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

S2FA: an accelerator automation framework for heterogeneous computing in datacenters.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Automated accelerator generation and optimization with composable, parallel and pipeline architecture.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Bandwidth Optimization Through On-Chip Memory Restructuring for HLS.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2016

When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 8th USENIX Workshop on Hot Topics in Cloud Computing, 2016

A quantitative analysis on microarchitectures of modern CPU-FPGA platforms.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

A Novel High-Throughput Acceleration Engine for Read Alignment.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Peng Wei

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