Keerthikumara Devarajegowda

According to our database1, Keerthikumara Devarajegowda authored at least 31 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
MetFI: Model-driven Fault Simulation Framework.
CoRR, 2022

Fast and Accurate Model-Driven FPGA-based System-Level Fault Emulation.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Design of a Tightly-Coupled RISC-V Physical Memory Protection Unit for Online Error Detection.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022

MetaFS: Model-driven Fault Simulation Framework.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2021
Model-based Generation of Assertions for Pre-silicon Verification.
PhD thesis, 2021

Aspect-Oriented Design Automation with Model Transformation.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Transformative Hardware Design Following the Model-Driven Architecture Vision.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Extending Verilator to Enable Fault Simulation.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

On Self-Verifying DSL Generation for Embedded Systems Automation.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2021

Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

ISA Modeling with Trace Notation for Context Free Property Generation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Accurate Cost Estimation of Memory Systems Utilizing Machine Learning and Solutions from Computer Vision for Design Automation.
IEEE Trans. Computers, 2020

Cost Estimation for Configurable Model-Driven SoC Designs Using Machine Learning.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Gap-free Processor Verification by S<sup>2</sup>QED and Property Generation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Using Machine Learning for predicting area and Firmware metrics of hardware designs from abstract specifications.
Microprocess. Microsystems, 2019

Towards a Python-Based One Language Ecosystem for Embedded Systems Automation.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019

How to Keep 4-Eyes Principle in a Design and Property Generation Flow.
Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

Formal Verification Methodology in an Industrial Setup.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Symbolic QED Pre-silicon Verification for Automotive Microcontroller Cores: Industrial Case Study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Embedded Systems' Automation following OMG's Model Driven Architecture Vision.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Increasing Soft Error Resilience by Software Transformation.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Meta-model Based Automation of Properties for Pre-Silicon Verification.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning.
Proceedings of the 8th International Workshop on Combinations of Intelligent Methods and Applications co-located with 30th International Conference on Artificial Intelligence Tools (ICTAI 2018), 2018

A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
The extendable translating instruction set simulator (ETISS) interlinked with an MDA framework for fast RISC prototyping.
Proceedings of the International Symposium on Rapid System Prototyping, 2017

Python based framework for HDSLs with an underlying formal semantics: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

On generation of properties from specification.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017


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