Esin Tureci

According to our database, Esin Tureci authored at least 14 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems.

Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff

CoRR, 2023

Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

CoRR, 2023

DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications.

Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff

CoRR, 2023

Microarchitectures for Heterogeneous Superconducting Quantum Computers.

Samuel Alexander Stein, Sara Sussman, Teague Tomesh, Charles Guinn, Esin Tureci, Sophia Fuhui Lin, Wei Tang, James A. Ang, Srivatsan Chakram, Ang Li, Margaret Martonosi, Frederic T. Chong, Andrew A. Houck, Isaac L. Chuang, Michael Austin DeMarco

CoRR, 2023

Massive Data-Centric Parallelism in the Chiplet Era.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

CoRR, 2023

HetArch: Heterogeneous Microarchitectures for Superconducting Quantum Systems.

Samuel Alexander Stein, Sara Sussman, Teague Tomesh, Charles Guinn, Esin Tureci, Sophia Fuhui Lin, Wei Tang, James A. Ang, Srivatsan Chakram, Ang Li, Margaret Martonosi, Fred Chong, Andrew A. Houck, Isaac L. Chuang, Michael Austin DeMarco

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Architectural Support for Optimizing Huge Page Selection Within the OS.

Aninda Manocha, Zi Yan, Esin Tureci, Juan L. Aragón, David W. Nellans, Margaret Martonosi

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022

The Implications of Page Size Management on Graph Analytics.

Aninda Manocha, Zi Yan, Esin Tureci, Juan L. Aragón, David W. Nellans, Margaret Martonosi

Proceedings of the IEEE International Symposium on Workload Characterization, 2022

2021

GraphAttack: Optimizing Data Supply for Graph Applications on In-Order Multicore Architectures.

Aninda Manocha, Tyler Sorensen, Esin Tureci, Opeoluwa Matthews, Juan L. Aragón, Margaret Martonosi

ACM Trans. Archit. Code Optim., 2021

2020

Foundations of empirical memory consistency testing.

Jake Kirkham, Tyler Sorensen, Esin Tureci, Margaret Martonosi

Proc. ACM Program. Lang., 2020

The MosaicSim Simulator (Full Technical Report).

Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi

CoRR, 2020

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems.

Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration.

Tyler Sorensen, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020