Marcelo Orenes-Vera

According to our database, Marcelo Orenes-Vera authored at least 17 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Muchisim: A Simulation Framework for Design Exploration of Multi-Chip Manycore Systems.

Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff

CoRR, 2023

Tascade: Hardware Support for Atomic-free, Asynchronous and Efficient Reduction Trees.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

CoRR, 2023

DCRA: A Distributed Chiplet-based Reconfigurable Architecture for Irregular Applications.

Marcelo Orenes-Vera, Esin Tureci, Margaret Martonosi, David Wentzlaff

CoRR, 2023

Using LLMs to Facilitate Formal Verification of RTL.

Marcelo Orenes-Vera, Margaret Martonosi, David Wentzlaff

CoRR, 2023

Massive Data-Centric Parallelism in the Chiplet Era.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

CoRR, 2023

AutoCC: Automatic Discovery of Covert Channels in Time-Shared Hardware.

Marcelo Orenes-Vera, Hyunsung Yun, Nils Wistoff, Gernot Heiser, Luca Benini, David Wentzlaff, Margaret Martonosi

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Wafer-Scale Fast Fourier Transforms.

Marcelo Orenes-Vera, Ilya Sharapov, Robert Schreiber, Mathias Jacquelin, Philippe Vandermersch, Sharan Chetlur

Proceedings of the 37th International Conference on Supercomputing, 2023

Dalorex: A Data-Local Program Execution and Architecture for Memory-bound Applications.

Marcelo Orenes-Vera, Esin Tureci, David Wentzlaff, Margaret Martonosi

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

DECADES: A 67mm², 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12nm FinFET.

Fei Gao, Ting-Jung Chang, Ang Li, Marcelo Orenes-Vera, Davide Giri, Paul J. Jackson, August Ning, Georgios Tziantzioulis, Joseph Zuckerman, Jinzheng Tu, Kaifeng Xu, Grigory Chirkov, Gabriele Tombesi, Jonathan Balkind, Margaret Martonosi, Luca P. Carloni, David Wentzlaff

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

CIFER: A 12nm, 16mm², 22-Core SoC with a 1541 LUT6/mm² 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA.

Ting-Jung Chang, Ang Li, Fei Gao, Tuan Ta, Georgios Tziantzioulis, Yanghui Ou, Moyang Wang, Jinzheng Tu, Kaifeng Xu, Paul J. Jackson, August Ning, Grigory Chirkov, Marcelo Orenes-Vera, Shady Agwa, Xiaoyu Yan, Eric Tang, Jonathan Balkind, Christopher Batten, David Wentzlaff

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

Cohort: Software-Oriented Acceleration for Heterogeneous SoCs.

Tianrui Wei, Nazerke Turtayeva, Marcelo Orenes-Vera, Omkar Lonkar, Jonathan Balkind

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Tiny but mighty: designing and realizing scalable latency tolerance for manycore SoCs.

Marcelo Orenes-Vera, Aninda Manocha, Jonathan Balkind, Fei Gao, Juan L. Aragón, David Wentzlaff, Margaret Martonosi

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

2021

RECITE: A framework for user trajectory analysis in cultural sites.

Marcelo Orenes-Vera, Fernando Terroso-Saenz, Mercedes Valdés-Vela

J. Ambient Intell. Smart Environ., 2021

AutoSVA: Democratizing Formal Verification of RTL Module Interactions.

Marcelo Orenes-Vera, Aninda Manocha, David Wentzlaff, Margaret Martonosi

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

The MosaicSim Simulator (Full Technical Report).

Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi

CoRR, 2020

MosaicSim: A Lightweight, Modular Simulator for Heterogeneous Systems.

Opeoluwa Matthews, Aninda Manocha, Davide Giri, Marcelo Orenes-Vera, Esin Tureci, Tyler Sorensen, Tae Jun Ham, Juan L. Aragón, Luca P. Carloni, Margaret Martonosi

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and Exploration.

Tyler Sorensen, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020