Faran Rafiq

According to our database, Faran Rafiq authored at least 3 papers between 2002 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology.

Ragh Kuttappa, Vinayak Honkote, Amreesh Rao, Gaurav Kamalkar, Kailash Chandrashekar, Eric Finley, Chaitanya Sankuratri, Faran Rafiq, Robert Orton, Nils Hernandez, Anuradha Srinivasan, Tanay Karnik

IEEE Solid State Circuits Lett., 2025

2003

Integrated floorplanning with buffer/channel insertion for bus-based designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

2002

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani

Proceedings of 2002 International Symposium on Physical Design, 2002