Tanay Karnik

According to our database1, Tanay Karnik authored at least 67 papers between 1994 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to error-tolerant circuits and near-load voltage regulators".

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

2018
Guest Editorial Low-Power, Adaptive Neuromorphic Systems: Devices, Circuit, Architectures and Algorithms.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Low-Power, Adaptive Neuromorphic Systems: Recent Progress and Future Directions.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM Based Last Level Cache.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Technology trends, requirements and challenges for ubiquitous self-powered IOT systems deployment.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Closed yet open DRAM: achieving low latency and high performance in DRAM memory systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Editorial.
IEEE Trans. VLSI Syst., 2017

2015
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design.
JETC, 2015

2014
Resiliency for many-core system on a chip.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance.
J. Solid-State Circuits, 2013

Adaptive and Resilient Circuits for Dynamic Variation Tolerance.
IEEE Design & Test, 2013

F5: Frequency generation and clock distribution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Power management and delivery for high-performance microprocessors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.
J. Solid-State Circuits, 2012

A 22nm dynamically adaptive clock distribution for voltage droop tolerance.
Proceedings of the Symposium on VLSI Circuits, 2012

Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Scaling the "Memory Wall": Designer track.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Design for test and reliability in ultimate CMOS.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.
IEEE Trans. on Circuits and Systems, 2011

Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.
J. Solid-State Circuits, 2011

A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.
J. Solid-State Circuits, 2011

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration.
IET Computers & Digital Techniques, 2011

Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

3DICs for tera-scale computing: a case study.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Coordinating 3D designs: Interface IP, standards or free form?
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.
J. Solid-State Circuits, 2010

A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Resilient microprocessor design for high performance & energy efficiency.
Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Opportunities for PMOS read and write ports in low voltage dual-port 8T bit cell arrays.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Resilient design in scaled CMOS for energy efficiency.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
SRAM dynamic stability estimation using MPFP and its applications.
Microelectron. J., 2009

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology.
J. Solid-State Circuits, 2009

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits.
J. Solid-State Circuits, 2009

Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance.
J. Solid-State Circuits, 2009

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters.
J. Solid-State Circuits, 2009

Resilient circuits - Enabling energy-efficient performance and reliability.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Circuit techniques for dynamic variation tolerance.
Proceedings of the 46th Design Automation Conference, 2009

2008
Thermal Via Allocation for 3-D ICs Considering Temporally and Spatially Variant Thermal Power.
IEEE Trans. VLSI Syst., 2008

Accurate Estimation of SRAM Dynamic Stability.
IEEE Trans. VLSI Syst., 2008

A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction.
J. Solid-State Circuits, 2008

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Analytical Model for the Propagation Delay of Through Silicon Vias.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
High Voltage Tolerant Linear Regulator With Fast Digital Control for Biasing of Integrated DC-DC Converters.
J. Solid-State Circuits, 2007

On-Die Supply-Resonance Suppression Using Band-Limited Active Damping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Low Voltage Buffered Bandgap Reference.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Power-efficient pulse width modulation DC/DC converters with zero voltage switching control.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

High-frequency DC-DC conversion : fact or fiction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Design of sub-90nm Circuits and Design Methodologies.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Logic soft errors in sub-65nm technologies design and CAD challenges.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes.
IEEE Trans. Dependable Sec. Comput., 2004

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

HiSIM: hierarchical interconnect-centric circuit simulator.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Design and reliability challenges in nanometer technologies.
Proceedings of the 41th Design Automation Conference, 2004

2003
Parameter variations and impact on circuits and microarchitecture.
Proceedings of the 40th Design Automation Conference, 2003

2002
Sub-90nm technologies: challenges and opportunities for CAD.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors.
Proceedings of the 39th Design Automation Conference, 2002

1999
Microprocessor Layout Method.
Proceedings of the VLSI Handbook., 1999

1995
An empirical model for accurate estimation of routing delay in FPGAs.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Structural and behavioral synthesis for testability techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994


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