Kailash Chandrashekar

According to our database, Kailash Chandrashekar authored at least 15 papers between 2008 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS.

Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton

IEEE J. Solid State Circuits, 2021

2020

25.5 A Self-Calibrated 1.2-to-3.8GHz 0.0052mm2 Synthesized Fractional-N MDLL Using a 2b Time-Period Comparator in 22nm FinFET CMOS.

Somnath Kundu, Likai Chai, Kailash Chandrashekar, Stefano Pellerano, Brent R. Carlton

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Transformer-Combining Digital PA with Efficiency Peaking at 0, -6, and -12 dB Backoff in 32nm CMOS.

Parmoon Seddighrad, Yorgos Palaskas, Hongtao Xu, Paolo Madoglio, Kailash Chandrashekar, David J. Allstot

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2017

13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications.

Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav A. Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A 32nm, 0.65-10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O.

William Y. Li, Hyung Seok Kim, Kailash Chandrashekar, Khoa Minh Nguyen, Ashoke Ravi

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2013

A Digital Fractional-N PLL With a PVT and Mismatch Insensitive TDC Utilizing Equivalent Time Sampling Technique.

Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Dan Shi, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi

IEEE J. Solid State Circuits, 2013

2012

A 2.4-GHz 20-40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS.

Ashoke Ravi, Paolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre-Hernandez, Masoud Sajadieh, J. E. Zarate-Roldan, Ofir Bochobza-Degani, Hasnain Lakdawala, Yorgos Palaskas

IEEE J. Solid State Circuits, 2012

A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.

Yulin Tan, Jon Duster, Chang-Tsung Fu, Erkan Alpman, Ajay Balankutty, Chun C. Lee, Ashoke Ravi, Stefano Pellerano, Kailash Chandrashekar, Hyung Seok Kim, Brent R. Carlton, Satoshi Suzuki, M. Shafi, Yorgos Palaskas, Hasnain Lakdawala

Proceedings of the Symposium on VLSI Circuits, 2012

A 20dBm 2.4GHz digital outphasing transmitter for WLAN application in 32nm CMOS.

Paolo Madoglio, Ashoke Ravi, Hongtao Xu, Kailash Chandrashekar, Marian Verhelst, Stefano Pellerano, Luis Cuellar, Mariano Aguirre, Masoud Sajadieh, Ofir B. Degani, Hasnain Lakdawala, Yorgos Palaskas

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 32nm CMOS all-digital reconfigurable fractional frequency divider for LO generation in multistandard SoC radios with on-the-fly interference management.

Kailash Chandrashekar, Stefano Pellerano, Paolo Madoglio, Ashoke Ravi, Yorgos Palaskas

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A digital fractional-N PLL with a 3mW 0.004mm² 6-bit PVT and mismatch insensitive TDC.

Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi

Proceedings of the 38th European Solid-State Circuit conference, 2012

2011

A 10 b 50 MS/s Opamp-Sharing Pipeline A/D With Current-Reuse OTAs.

Kailash Chandrashekar, Bertan Bakkaloglu

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling.

Kailash Chandrashekar, Marco Corsi, John W. Fattaruso, Bertan Bakkaloglu

IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009

A 10b 50MS/s opamp-sharing pipeline A/D with current-reuse OTAs.

Kailash Chandrashekar, Bertan Bakkaloglu

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008

A fully integrated pulsed-LASER time-of-flight measurement system with 12ps single-shot precision.

Tino Copani, Bert Vermeire, Anuj Jain, Habib Karaki, Kailash Chandrashekar, Sushmit Goswami, Jennifer Kitchen, Hoon Hee Chung, Ilker Deligoz, Bertan Bakkaloglu, Hugh J. Barnaby, Sayfe Kiaei

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008