Naveed A. Sherwani

According to our database, Naveed A. Sherwani authored at least 50 papers between 1989 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2009

Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs.

Naveed A. Sherwani

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2005

DFM rules!

Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan

Proceedings of the 42nd Design Automation Conference, 2005

2003

Integrated floorplanning with buffer/channel insertion for bus-based designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

COT - customer owned trouble.

Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta

Proceedings of the 40th Design Automation Conference, 2003

2002

Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.

Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani

Proceedings of 2002 International Symposium on Physical Design, 2002

2000

On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs.

Dinesh P. Mehta, Naveed A. Sherwani

ACM Trans. Design Autom. Electr. Syst., 2000

EDA challenges facing future microprocessor design.

T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

The bottom-10 problems in EDA (panel session (title only)).

Naveed A. Sherwani

Proceedings of the 2000 International Symposium on Physical Design, 2000

1999

SRC physical design top ten problem.

Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout

Proceedings of the 1999 International Symposium on Physical Design, 1999

Integrated floorplanning and interconnect planning.

Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998

Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout.

Naveed A. Sherwani, Prashant Sawkar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

T3: Physical Design.

Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Optimal algorithms for planar over-the-cell routing problems.

Srinivasa R. Danda, Xiaolin Liu, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A Minimum-Area Floorplanning Algorithm for MBC Designs.

Dinesh P. Mehta, Naveed A. Sherwani

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

Optimal algorithms for planar over-the-cell routing in the presence of obstacles.

Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

OPRON: a new approach to planar OTC routing.

Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, Aman Sureka

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994

Incomplete hypercubes: Algorithms and embeddings.

Alfred J. Boals, Ajay K. Gupta, Naveed A. Sherwani

J. Supercomput., 1994

High Performance Over-the-Cell Routing.

Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani

Proceedings of the Seventh International Conference on VLSI Design, 1994

Over-the-Cell Routing Algorithms for Industrial Cell Models.

Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani

Proceedings of the Seventh International Conference on VLSI Design, 1994

An Efficient Four Layer Over-the-Cell Router.

Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Hierarchical Approach to Clock Routing in High Performance Systems.

Wasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Comparative Analysis of New CMOS Leaf Cells for OTC Routing.

Pramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Floorplanning for mixed macro block and standard cell designs.

Arun Shanbhag, Srinivasa R. Danda, Naveed A. Sherwani

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

An optimal algorithm for maximum two planar subset problem [VLSI layout].

Anand Panyam, Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Algorithmic Aspects of Three Dimensional MCM Routing.

Qiong Yu, Sandeep Badida, Naveed A. Sherwani

Proceedings of the 31st Conference on Design Automation, 1994

A Unified Approach to Multilayer Over-the-Cell Routing.

Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam

Proceedings of the 31st Conference on Design Automation, 1994

1993

Middle terminal cell models for efficient over-the-cell routing in high-performance circuits.

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani

IEEE Trans. Very Large Scale Integr. Syst., 1993

Utilization of vacant terminals for improved over-the-cell channel routing.

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

A provably good multilayer topological planar routing algorithm in IC layout designs.

Jason Cong, Moazzem Hossain, Naveed A. Sherwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Programmable multichip modules.

Surendra Burman, Naveed A. Sherwani

IEEE Micro, 1993

Efficient Edge Domination Problems in Graphs.

Dana L. Grinstead, Peter J. Slater, Naveed A. Sherwani, Nancy D. Holmes

Inf. Process. Lett., 1993

A Provably Good Algorithm for <i>k</i>-Layer Topological Planar Routing Problems.

Jason Cong, Moazzem Hossain, Naveed A. Sherwani

Proceedings of the Sixth International Conference on VLSI Design, 1993

On Optimum Cell Models for Over-the-Cell Routing.

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani

Proceedings of the Sixth International Conference on VLSI Design, 1993

Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model.

Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Algorithms for VLSI physical design automation.

Naveed A. Sherwani

Kluwer, ISBN: 978-0-7923-9294-1, 1993

1992

A Parallel Algorithm for Single Row Routing Problems.

Arnob Roy, Jitender S. Deogun, Naveed A. Sherwani

J. Circuits Syst. Comput., 1992

Zero skew clock routing in multiple-clock synchronous systems.

Wasim Khan, Moazzem Hossain, Naveed A. Sherwani

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

New channel segmentation model and associated routing algorithm for high performance FPGAs.

Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Over-the-Cell Routers for New Cell Model.

Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh

Proceedings of the 29th Design Automation Conference, 1992

Over-the-Cell Channel Routing for High Performance Circuits.

Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh

Proceedings of the 29th Design Automation Conference, 1992

1991

Fully Normal Algorithms for Incomplete Hypercubes.

Venkata K. Prabhala, Naveed A. Sherwani

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

On Optimal Embeddings into Incomplete Hypercubes.

Ajay Gupta, Alfred J. Boals, Naveed A. Sherwani

Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

An Efficient Approximation Algorithm for Hypercube Scheduling.

Alfred J. Boals, Ajay Gupta, Jahangir A. Hashmi, Naveed A. Sherwani

Proceedings of the Advances in Computing and Information, 1991

Compact Hypercubes: Properties and Recognition.

Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani

Proceedings of the Advances in Computing and Information, 1991

Switchbox Steiner Tree Problem in Presence of Obstacles.

S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

On Topological Via Minimization and Routing.

Moazzem Hossain, Naveed A. Sherwani

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Algorithms for Three-Layer Over-The-Cell Channel Routing.

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals.

Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh

Proceedings of the 28th Design Automation Conference, 1991

1990

MISER: An Integrated Three Layer Gridless Channel Router and Compactor.

Roshan A. Gidwani, Naveed A. Sherwani

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

A New Heuristic for Single Row Routing Problems.

Naveed A. Sherwani, Jitender S. Deogun

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989