Farshid Aryanfar

According to our database1, Farshid Aryanfar authored at least 5 papers between 2010 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2017
A 28-GHz SiGe BiCMOS PA With 32% Efficiency and 23-dBm Output Power.
IEEE J. Solid State Circuits, 2017

2015
A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators.
IEEE J. Solid State Circuits, 2015

2011
A Multiband Transceiver System in 45-nm CMOS for Extended Data Rate through Notchy Wireline Channels.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2010
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Low-skew clock distribution using zero-phase-clock-buffer DLLs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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