Reza Navid

According to our database1, Reza Navid authored at least 9 papers between 2003 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators.
IEEE J. Solid State Circuits, 2015

2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2010
Circuit-Based Characterization of Device Noise Using Phase Noise Data.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2007
A Circuit-Based Noise Parameter Extraction Technique for MOSFETs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005
An analytical formulation of phase noise of signals with Gaussian-distributed jitter.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Minimum achievable phase noise of RC oscillators.
IEEE J. Solid State Circuits, 2005

2003
Lumped, inductorless oscillators: how far can they go? [phase noise reduction limit].
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003


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