Ting Wu

According to our database, Ting Wu authored at least 12 papers between 2005 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.

Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.

Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

2010

Architectural Comparison of Analog and Digital Duty Cycle Corrector for High Speed I/O Link.

Leneesh Raghavan, Ting Wu

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Low-skew clock distribution using zero-phase-clock-buffer DLLs.

Ting Wu, Farshid Aryanfar, Haechang Lee, Jie Shen, T. J. Chin, Carl W. Werner, Ken Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers.

Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon

IEEE J. Solid State Circuits, 2009

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.

Haechang Lee, Kun-Yung Ken Chang, Jung-Hoon Chun, Ting Wu, Yohan Frans, Brian S. Leibowitz, Nhat Nguyen, T. J. Chin, Kambiz Kaviani, Jie Shen, Xudong Shi, Wendemagegnehu T. Beyene, Simon Li, Reza Navid, Marko Aleksic, Fred S. Lee, Fredy Quan, Jared Zerbe, Rich Perego, Fariborz Assaderaghi

IEEE J. Solid State Circuits, 2009

2008

Clocking circuits for a 16Gb/s memory interface.

Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung-Hoon Chun, T. J. Chin, Jie Shen, Rich Perego, Ken Chang

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Noise tolerant oscillator design using perturbation projection vector analysis.

Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators.

Ting Wu, Kartikeya Mayaram, Un-Ku Moon

IEEE J. Solid State Circuits, 2007

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop.

Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Dependence of LC VCO oscillation frequency on bias current.

Ting Wu, Un-Ku Moon, Kartikeya Mayaram

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications.

Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005