Amir Amirkhany

Orcid: 0000-0002-4377-6947

According to our database1, Amir Amirkhany authored at least 27 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process.
IEEE J. Solid State Circuits, 2022

Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2022

2021
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Baud rate pattern-adaptable dual loop clock recovery for high speed serial links.
Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2019
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2016
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver.
IEEE J. Solid State Circuits, 2013

A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.
IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.
IEEE J. Solid State Circuits, 2012

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link.
IEEE J. Solid State Circuits, 2012

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Power-efficient I/O design considerations for high-bandwidth applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

On overcoming the limitations of single-ended signaling for graphics memory interfaces.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.
IEEE J. Solid State Circuits, 2010

2009
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.
IEEE J. Solid State Circuits, 2008

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter.
IEEE J. Solid State Circuits, 2008

2007
Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links.
Proceedings of IEEE International Conference on Communications, 2007

A new technique for characterization of digital-to-analog converters in high-speed systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Time-Variant Characterization and Compensation of Wideband Circuits.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links.
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006

2004
Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication.
Proceedings of IEEE International Conference on Communications, 2004

Multi-tone signaling for high-speed backplane electrical links.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004


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