Tomokazu Yoneda

According to our database, Tomokazu Yoneda authored at least 56 papers between 2001 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell.

Mahshid Mojtabavi Naeini, Sreedharan Baskara Dass, Chia Yee Ooi, Tomokazu Yoneda, Michiko Inoue

Integr., 2017

An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan.

Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue

IEICE Trans. Inf. Syst., 2017

Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.

Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu

Proceedings of the 22nd IEEE European Test Symposium, 2017

Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.

Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue

IEICE Trans. Inf. Syst., 2016

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Memory block based scan-BIST architecture for application-dependent FPGA testing.

Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units.

Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012

A Failure Prediction Strategy for Transistor Aging.

Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara

IEEE Trans. Very Large Scale Integr. Syst., 2012

Test Pattern Ordering and Selection for High Quality Test Set under Constraints.

Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2012

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.

Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue

Proceedings of the 2012 IEEE International Test Conference, 2012

DART: Dependable VLSI test architecture and its implementation.

Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Delay Testing: Improving Test Quality and Avoiding Over-testing.

Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda

IPSJ Trans. Syst. LSI Des. Methodol., 2011

Balanced Secure Scan: Partial Scan Approach for Secret Information Protection.

Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara

J. Electron. Test., 2011

Faster-than-at-speed test for increased test quality and in-field reliability.

Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara

Proceedings of the 2011 IEEE International Test Conference, 2011

Temperature-Variation-Aware Test Pattern Optimization.

Tomokazu Yoneda, Makoto Nakao, Michiko Inoue, Yasuo Sato, Hideo Fujiwara

Proceedings of the 16th European Test Symposium, 2011

2010

Design and Optimization of Transparency-Based TAM for SoC Test.

Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2010

Thermal-uniformity-aware X-filling to reduce temperature-induced delay variation for accurate at-speed testing.

Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Hideo Fujiwara

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Aging test strategy and adaptive test scheduling for SoC failure prediction.

Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Test pattern selection to optimize delay test quality with a limited size of test set.

Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara

Proceedings of the 15th European Test Symposium, 2010

Seed Ordering and Selection for High Quality Delay Test.

Tomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara

Proceedings of the 19th IEEE Asian Test Symposium, 2010

RedSOCs-3D: Thermal-safe test scheduling for 3D-stacked SOC.

Fawnizu Azmadi Hussin, Thomas Edison Yu, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Partial Scan Approach for Secret Information Protection.

Michiko Inoue, Tomokazu Yoneda, Muneo Hasegawa, Hideo Fujiwara

Proceedings of the 14th IEEE European Test Symposium, 2009

Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.

Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.

Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Test Scheduling for Multi-Clock Domain SoCs under Power Constraint.

Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Scheduling Power-Constrained Tests through the SoC Functional Bus.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

NoC-Compatible Wrapper Design and Optimization under Channel-Bandwidth and Test-Time Constraints.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects.

Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the Design, Automation and Test in Europe, 2008

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.

Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.

Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

TAM Design and Optimization for Transparency-Based SoC Test.

Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.

Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 12th European Test Symposium, 2007

Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers.

Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

A DFT Method for Time Expansion Model at Register Transfer Level.

Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 44th Design Automation Conference, 2007

Thermal-Safe Test Access Mechanism and Wrapper Co-optimization for System-on-Chip.

Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

Test Scheduling for Memory Cores with Built-In Self-Repair.

Tomokazu Yoneda, Yuusuke Fukuda, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

Area Overhead and Test Time Co-Optimization through NoC Bandwidth Sharing.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Design for consecutive transparency method of RTL circuits.

Tomokazu Yoneda, Hideo Fujiwara

Syst. Comput. Jpn., 2006

A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips.

Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2006

Power-Constrained SOC Test Schedules through Utilization of Functional Buses.

Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Power-constrained test scheduling for multi-clock domain SoCs.

Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A memory grouping method for sharing memory BIST logic.

Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability.

Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

An efficient scan tree design for test time reduction.

Yannick Bonhomme, Tomokazu Yoneda, Hideo Fujiwara, Patrick Girard

Proceedings of the 9th European Test Symposium, 2004

2003

Design for Consecutive Transparency of Cores in System-on-a-Chip.

Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability.

Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.

Tomokazu Yoneda, Hideo Fujiwara

J. Electron. Test., 2002

2001

A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability.

Tomokazu Yoneda, Hideo Fujiwara

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001