Luis Piñuel
Orcid: 0000-0002-3049-828X
According to our database1,
Luis Piñuel
authored at least 57 papers
between 1998 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Improving the Representativeness of Simulation Intervals for the Cache Memory System.
IEEE Access, 2024
2023
Automatic Generation of Micro-kernels for Performance Portability of Matrix Multiplication on RISC-V Vector Processors.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
IEEE Trans. Emerg. Top. Comput., 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021
2020
Spatio-Temporal Resolution of Irradiance Samples in Machine Learning Approaches for Irradiance Forecasting.
IEEE Access, 2020
Proceedings of the Cloud Computing, Big Data & Emerging Topics - 8th Conference, 2020
2018
Short term cloud nowcasting for a solar power plant based on irradiance historical data.
J. Comput. Sci. Technol., 2018
2017
2015
Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors.
CoRR, 2015
Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study.
Comput. Electr. Eng., 2015
Balancing task- and data-level parallelism to improve performance and energy consumption of matrix computations on the Intel Xeon Phi.
Comput. Electr. Eng., 2015
2014
2013
Reducing writes in phase-change memory environments by using efficient cache replacement policies.
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets.
J. Circuits Syst. Comput., 2012
2011
IET Comput. Digit. Tech., 2011
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011
2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
2009
IEEE Trans. Computers, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting.
IEEE Trans. Parallel Distributed Syst., 2008
IET Comput. Digit. Tech., 2008
Proceedings of the Euro-Par 2008, 2008
2006
J. Low Power Electron., 2006
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Substituting associative load queue with simple hash tables in out-of-order microprocessors.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Pack Transposition: Enhancing Superword Level Parallelism Exploitation.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
JPEG2000 Optimization in General Purpose Microprocessors.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
2004
IEEE Des. Test Comput., 2004
Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.
Proceedings of the High Performance Computing for Computational Science, 2004
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
2003
IEEE Micro, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the Embedded Software for SoC, 2003
2002
SIGARCH Comput. Archit. News, 2002
Proceedings of the High Performance Computing for Computational Science, 2002
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.
Proceedings of the High Performance Computing, 2002
2001
J. Syst. Archit., 2001
2000
Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance.
Proceedings of the Vector and Parallel Processing, 2000
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000
Proceedings of the 26th EUROMICRO 2000 Conference, 2000
1999
Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
1998
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998