Tetsuya Fujita

According to our database1, Tetsuya Fujita authored at least 12 papers between 1988 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2013
Improvement of Factor Model with Text Information Based on Factor Model Construction Process.
Proceedings of the Intelligent Interactive Multimedia Systems and Services, 2013

2011
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits, 2011

A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

2010
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications.
IEEE J. Solid State Circuits, 2009

Learning of situation dependent prediction toward acquiring physical causality.
Proceedings of the Ninth International Conference on Epigenetic Robotics (EpiRob 2009), 2009

2008
A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006
Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

1996
Substrate noise influence on circuit performance in variable threshold-voltage scheme.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1988
MASA: A Multithreaded Processor Architecture for Parallel Symbolic Computing.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988


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