Hideho Arakida

According to our database, Hideho Arakida authored at least 14 papers between 1998 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

Visconti2 - a heterogeneous multi-core SoC for image-recognition applications.

Masato Uchiyama, Hideho Arakida, Yasuki Tanabe, Tsukasa Ike, Takanori Tamai, Moriyasu Banno

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2011

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki

IEEE J. Solid State Circuits, 2011

2010

A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.

Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Yukihito Oowaki

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications.

Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi

IEEE J. Solid State Circuits, 2009

Design and implementation of scalable, transparent threads for multi-core media processor.

Takeshi Kodaka, Shunsuke Sasaki, Takahiro Tokuyoshi, Ryuichiro Ohyama, Nobuhiro Nonogaki, Koji Kitayama, Tatsuya Mori, Yasuyuki Ueda, Hideho Arakida, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi, Nobu Matsumoto

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Comparative evaluation of memory models for chip multiprocessors.

Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis

ACM Trans. Archit. Code Optim., 2008

2007

Comparing memory systems for chip multiprocessors.

Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis

Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006

A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling.

Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama

IEEE J. Solid State Circuits, 2006

2001

A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology.

Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Tohru Furuyama

Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

2000

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM.

Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama

IEEE J. Solid State Circuits, 2000

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications.

Masafumi Takahashi, Tsuyoshi Nishikawa, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Matsumoto, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Junya Shirakura, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tohru Furuyama

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.

Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama

IEEE J. Solid State Circuits, 1998

Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.

Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda

Proceedings of the 35th Conference on Design Automation, 1998

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.

Mototsugu Hamada, Masafumi Takahashi, Hideho Arakida, Akihiko Chiba, Toshihiro Terazawa, Takashi Ishikawa, Masahiro Kanazawa, Mutsunori Igarashi, Kimiyoshi Usami, Tadahiro Kuroda

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998