Hideho Arakida

According to our database1, Hideho Arakida authored at least 9 papers between 1998 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2011
A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM.
IEEE J. Solid State Circuits, 2011

2010
A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications.
IEEE J. Solid State Circuits, 2009

Design and implementation of scalable, transparent threads for multi-core media processor.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Comparative evaluation of memory models for chip multiprocessors.
ACM Trans. Archit. Code Optim., 2008

2007
Comparing memory systems for chip multiprocessors.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2001
A Single-Chip Low-Power Mpeg-4 Audiovisual Lsi Using Embedded Dram Technology.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

2000
A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998


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