Toshihiro Terazawa

According to our database1, Toshihiro Terazawa authored at least 6 papers between 1998 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2009
A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications.
IEEE J. Solid State Circuits, 2009

2000
A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM.
IEEE J. Solid State Circuits, 2000

A scalable MPEG-4 video codec architecture for IMT-2000 multimedia applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998
A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.
IEEE J. Solid State Circuits, 1998

Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.
Proceedings of the 35th Conference on Design Automation, 1998

A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme.
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998


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