Daniel K. Beece

According to our database1, Daniel K. Beece
  • authored at least 13 papers between 1984 and 2010.
  • has a "Dijkstra number"2 of four.

Timeline

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Article 
PhD thesis 
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Links

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Bibliography

2010
Transistor sizing of custom high-performance digital circuits with parametric yield considerations.
Proceedings of the 47th Design Automation Conference, 2010

2006
First-Order Incremental Block-Based Statistical Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

2005
Verification strategy for the Blue Gene/L chip.
IBM Journal of Research and Development, 2005

2003
Formal verification - prove it or pitch it.
Proceedings of the 40th Design Automation Conference, 2003

2002
An overview of the BlueGene/L Supercomputer.
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Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002


2001
Blue Gene: A vision for protein science using a petaflop supercomputer.
IBM Systems Journal, 2001

1997
Design Methodology for the High-Performance G4 S/390.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1990
The EVE companion simulator.
Proceedings of the European Design Automation Conference, 1990

1988
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

The IBM Engineering Verification Engine.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1986
SLS - a fast switch level simulator for verification and fault coverage analysis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, NV, June, 1986., 1986

1984
Using a Hardware Simulation Engine for Custom MOS Structured Designs.
IBM Journal of Research and Development, 1984


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