Gary S. Ditlow

According to our database, Gary S. Ditlow authored at least 8 papers between 1984 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.

Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2007

Structured and tuned array generation (STAG) for high-performance random logic.

Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

1999

Integrated Manufacturing and Development (IMaD).

David Moran, Gary S. Ditlow, Daria Dooling, Ralph Williams, Tom Wilkins

Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

Parallel Analysis of IC Power Distribution Networks.

Gary S. Ditlow, Anshul Gupta, Richard L. Moore, David Moran, Ralph Williams, Tom Wilkins

Proceedings of the Ninth SIAM Conference on Parallel Processing for Scientific Computing, 1999

1992

HLSIM-a new hierarchical logic simulator in APL.

David A. Zein, Oliver P. Engel, Gary S. Ditlow

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

Algorithms for the design verification of bipolar array chips.

David A. Zein, Oliver P. Engel, Gary S. Ditlow

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

HLSIM - A New Hierarchical Logic Simulator and Netlist Converter.

David A. Zein, Oliver P. Engel, Gary S. Ditlow

Proceedings of the 29th Design Automation Conference, 1992

1984

Random Pattern Testability.

Jacob Savir, Gary S. Ditlow, Paul H. Bardell

IEEE Trans. Computers, 1984