Sebastian Ehrenreich
According to our database1,
Sebastian Ehrenreich
authored at least 4 papers
between 2006 and 2011.
Collaborative distances:
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Bibliography
2011
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2008
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V.
IEEE J. Solid State Circuits, 2008
2007
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006