Robert K. Montoye

According to our database1, Robert K. Montoye authored at least 30 papers between 1981 and 2021.

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Bibliography

2021

2017

2014
1 Mb 0.41 µm<sup>2</sup> 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing.
IEEE J. Solid State Circuits, 2014

Matrix-matrix multiplication on a large register file architecture with indirection.
Proceedings of the 21st International Conference on High Performance Computing, 2014

2013
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Processor architecture for software implementation of multi-sector G-RAKE receivers for HSUPA wireless infrastructure.
Proceedings of the IEEE International Conference on Acoustics, 2013

2012
Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

2011
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 270ps 20mW 108-bit End-around Carry Adder for Multiply-Add Fused Floating Point Unit.
J. Signal Process. Syst., 2010

Practical Strategies for Power-Efficient Computing Technologies.
Proc. IEEE, 2010

Performance and power evaluation of an in-line accelerator.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2008
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.
IEEE J. Solid State Circuits, 2008

Custom is from Venus and synthesis from Mars.
Proceedings of the 45th Design Automation Conference, 2008

2006
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM J. Res. Dev., 2006

Gate-Induced Barrier Field Effect Transistor (GBFET) - A New Thin Film Transistor for Active Matrix Liquid Crystal Display Systems.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Circuit Design Style for Energy Efficiency: LSDL and Compound Domino.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

VICTORIA: VMX indirect compute technology oriented towards in-line acceleration.
Proceedings of the Third Conference on Computing Frontiers, 2006

2005
Testing and debugging delay faults in dynamic circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Controlled-Load Limited Switch Dynamic Logic Circuit.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004
The four degrees of 3D.
Proceedings of the 2004 International Symposium on Physical Design, 2004

A low latency and low power dynamic Carry Save Adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

1998
A decompression core for PowerPC.
IBM J. Res. Dev., 1998

1990
Design of the IBM RISC System/6000 Floating-Point Execution Unit.
IBM J. Res. Dev., 1990

Leading-Zero Anticipator (LZA) in the IBM RISC System/6000 Floating-Point Execution Unit.
IBM J. Res. Dev., 1990

The IBM RISC System/6000 Processor: Hardware Overview.
IBM J. Res. Dev., 1990

IBM second-generation RISC machine organization.
Proceedings of the Intellectual Leverage: Thirty-Fifth IEEE Computer Society International Conference, 1990

1984
Optimization and Testing of Nmos Arithmetic Structures (Vlsi, Mos)
PhD thesis, 1984

1982
A Practical Algorithm for the Solution of Triangular Systems on a Parallel Processing System.
IEEE Trans. Computers, 1982

1981
Area-time efficient addition in charge based technology.
Proceedings of the 18th Design Automation Conference, 1981


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