Leland Chang
According to our database1,
Leland Chang
authored at least 50 papers
between 2003 and 2024.
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Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
IEEE Micro, 2019
Proceedings of the IEEE International Symposium on Workload Characterization, 2019
Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019
BiScaled-DNN: Quantizing Long-tailed Datastructures with Two Scale Factors for Deep Neural Networks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Session 30 overview: Emerging memories: Memory and technology directions subcommittees.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errors.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017
2016
A Low Ripple Switched-Capacitor Voltage Regulator Using Flying Capacitance Dithering.
IEEE J. Solid State Circuits, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
A fully-integrated 40-phase flying-capacitance-dithered switched-capacitor voltage regulator with 6mV output ripple.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
1 Mb 0.41 µm<sup>2</sup> 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs).
IEEE Trans. Very Large Scale Integr. Syst., 2013
A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2011
IEEE Des. Test Comput., 2011
Future system and memory architectures: Transformations by technology and applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
2008
An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches.
IEEE J. Solid State Circuits, 2008
2006
2003