Bruce M. Fleischer

According to our database, Bruce M. Fleischer authored at least 20 papers between 1996 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.

Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim, Siyu Koswatta, Martin Lutz, Alberto Mannari, Abey Mathew, Indira Nair, Ashish Ranjan, Zhibin Ren, Scot Rider, Thomas Roewer, David L. Satterfield, Marcel Schaal, Sanchari Sen, Gustavo Tellez, Hung Tran, Wei Wang, Vidhi Zalani, Jintao Zhang, Xin Zhang, Vinay Shah, Robert M. Senger, Arvind Kumar, Pong-Fei Lu, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022

A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.

Sae Kyu Lee, Ankur Agrawal, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matthew Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, Monodeep Kar, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

IEEE J. Solid State Circuits, 2022

2021

A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.

Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim, Yulong Li, Zhibin Ren, Scot Rider, Marcel Schaal, Kerstin Schelm, Michael Scheuermann, Xiao Sun, Hung Tran, Naigang Wang, Wei Wang, Xin Zhang, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun, Naigang Wang, Chia-Yu Chen, Allison Allain, James Bonanno, Nianzheng Cao, Robert Casatuta, Matthew Cohen, Bruce M. Fleischer, Michael Guillorn, Howard Haynie, Jinwook Jung, Mingu Kang, Kyu-Hyoun Kim, Siyu Koswatta, Sae Kyu Lee, Martin Lutz, Silvia M. Mueller, Jinwook Oh, Ashish Ranjan, Zhibin Ren, Scot Rider, Kerstin Schelm, Michael Scheuermann, Joel Silberman, Jie Yang, Vidhi Zalani, Xin Zhang, Ching Zhou, Matthew M. Ziegler, Vinay Shah, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Leland Chang, Kailash Gopalakrishnan

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020

Efficient AI System Design With Cross-Layer Approximate Computing.

Swagath Venkataramani, Xiao Sun, Naigang Wang, Chia-Yu Chen, Jungwook Choi, Mingu Kang, Ankur Agarwal, Jinwook Oh, Shubham Jain, Tina Babinsky, Nianzheng Cao, Thomas W. Fox, Bruce M. Fleischer, George Gristede, Michael Guillorn, Howard Haynie, Hiroshi Inoue, Kazuaki Ishizaki, Michael J. Klaiber, Shih-Hsien Lo, Gary W. Maier, Silvia M. Mueller, Michael Scheuermann, Eri Ogawa, Marcel Schaal, Mauricio J. Serrano, Joel Silberman, Christos Vezyrtzis, Wei Wang, Fanchieh Yee, Jintao Zhang, Matthew M. Ziegler, Ching Zhou, Moriyoshi Ohara, Pong-Fei Lu, Brian W. Curran, Sunil Shukla, Vijayalakshmi Srinivasan, Leland Chang, Kailash Gopalakrishnan

Proc. IEEE, 2020

A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.

Jinwook Oh, Sae Kyu Lee, Mingu Kang, Matthew M. Ziegler, Joel Silberman, Ankur Agrawal, Swagath Venkataramani, Bruce M. Fleischer, Michael Guillorn, Jungwook Choi, Wei Wang, Silvia M. Mueller, Shimon Ben-Yehuda, James Bonanno, Nianzheng Cao, Robert Casatuta, Chia-Yu Chen, Matt Cohen, Ophir Erez, Thomas W. Fox, George Gristede, Howard Haynie, Vicktoria Ivanov, Siyu Koswatta, Shih-Hsien Lo, Martin Lutz, Gary W. Maier, Alex Mesh, Yevgeny Nustov, Scot Rider, Marcel Schaal, Michael Scheuermann, Xiao Sun, Naigang Wang, Fanchieh Yee, Ching Zhou, Vinay Shah, Brian W. Curran, Vijayalakshmi Srinivasan, Pong-Fei Lu, Sunil Shukla, Kailash Gopalakrishnan, Leland Chang

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.

Ankur Agrawal, Bruce M. Fleischer, Silvia M. Mueller, Xiao Sun, Naigang Wang, Jungwook Choi, Kailash Gopalakrishnan

Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019

2018

A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.

Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Across the Stack Opportunities for Deep Learning Acceleration.

Vijayalakshmi Srinivasan, Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan

Proceedings of the International Symposium on Low Power Electronics and Design, 2018

2016

Synthesis design strategies for energy-efficient microprocessors.

Ching Zhou, Yu-Shiang Lin, Pong-Fei Lu, Bruce M. Fleischer, David J. Frank, Leland Chang

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

A statistical critical path monitor in 14nm CMOS.

Bruce M. Fleischer, Christos Vezyrtzis, Karthik Balakrishnan, Keith A. Jenkins

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Active Memory Cube: A processing-in-memory architecture for exascale systems.

Ravi Nair, Samuel Antão, Carlo Bertolli, Pradip Bose, José R. Brunheroto, Tong Chen, Chen-Yong Cher, Carlos H. A. Costa, J. Doi, Constantinos Evangelinos, Bruce M. Fleischer, Thomas W. Fox, Diego S. Gallo, Leopold Grinberg, John A. Gunnels, Arpith C. Jacob, P. Jacob, Hans M. Jacobson, Tejas Karkhanis, C. Kim, Jaime H. Moreno, John K. O'Brien, Martin Ohmacht, Yoonho Park, Daniel A. Prener, Bryan S. Rosenburg, Kyung Dong Ryu, Olivier Sallenave, Mauricio J. Serrano, P. D. M. Siegl, Krishnan Sugavanam, Zehra Sura

IBM J. Res. Dev., 2015

2013

Low-Cost Concurrent Error Detection for Floating-Point Unit (FPU) Controllers.

Michail Maniatakos, Prabhakar Kudva, Bruce M. Fleischer, Yiorgos Makris

IEEE Trans. Computers, 2013

2011

Exponent monitoring for low-cost concurrent error detection in FPU control logic.

Michail Maniatakos, Yiorgos Makris, Prabhakar Kudva, Bruce M. Fleischer

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.

Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

64-bit prefix adders: Power-efficient topologies and design solutions.

Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006

4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.

Brian W. Curran, Bradley D. McCredie, Leonid Sigal, Eric M. Schwarz, Bruce M. Fleischer, Yuen H. Chan, D. Webber, Vaden Vaden, A. Goyal

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

The IBM eServer z990 floating-point unit.

Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess, Christopher A. Krygowski, Bruce M. Fleischer, Michael Kroener

IBM J. Res. Dev., 2004

2001

Blue Gene: A vision for protein science using a petaflop supercomputer.

Frances E. Allen, George S. Almási, Wanda Andreoni, Daniel K. Beece, Bruce J. Berne, Arthur A. Bright, José R. Brunheroto, Calin Cascaval, José G. Castaños, Paul Coteus, Paul Crumley, Alessandro Curioni, Monty Denneau, Wilm E. Donath, Maria Eleftheriou, Blake G. Fitch, Bruce M. Fleischer, Christos J. Georgiou, Robert S. Germain, Mark Giampapa, Donna L. Gresh, Manish Gupta, Ruud A. Haring, C. T. Howard Ho, Peter H. Hochschild, Susan Flynn Hummel, Tiziana Jonas, Derek Lieber, Glenn J. Martyna, Kiran K. Maturu, José E. Moreira, Dennis M. Newns, Matthew Newton, Robert Philhower, Thomas Picunko, Jed W. Pitera, Michael Pitman, Rick A. Rand, Ajay K. Royyuru, Valentina Salapura, Alda Sanomiya, Rahul S. Shah, Yuk Yin Sham, Sarabjeet Singh, Marc Snir, Frank Suits, Richard A. Swetz, William C. Swope, Nagesh K. Vishnumurthy, T. J. Christopher Ward, Henry S. Warren Jr., Ruhong Zhou

IBM Syst. J., 2001

1996

Static timing analysis for self resetting circuits.

Vinod Narayanan, Barbara A. Chappell, Bruce M. Fleischer

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996