Lizhou Wu

Orcid: 0000-0002-5883-2251

According to our database1, Lizhou Wu authored at least 32 papers between 2015 and 2024.

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Bibliography

2024
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow.
ACM Trans. Design Autom. Electr. Syst., March, 2024

2023
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

An improved matrix split-iteration method for analyzing underground water flow.
Eng. Comput., 2023

A Hybrid Kernel Pruning Approach for Efficient and Accurate CNNs.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

Optimizing the Parallelism of Communication and Computation in Distributed Training Platform.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2023

2022
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs.
IEEE Trans. Computers, 2022

Defects, Fault Modeling, and Test Development Framework for RRAMs.
ACM J. Emerg. Technol. Comput. Syst., 2022

Special Session: STT-MRAMs: Technology, Design and Test.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

SpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-Tree.
Proceedings of the Network and Parallel Computing, 2022

Recent Trends and Perspectives on Defect-Oriented Testing.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

PM-based Persistent Key Value Stores: a Survey.
Proceedings of the 5th International Conference on Data Science and Information Technology, 2022

2021
Hard-to-Detect Fault Analysis in FinFET SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Defect and Fault Modeling Framework for STT-MRAM Testing.
IEEE Trans. Emerg. Top. Comput., 2021

A novel mathematical model for predicting landslide displacement.
Soft Comput., 2021

An improved whale optimization algorithm for locating critical slip surface of slopes.
Adv. Eng. Softw., 2021

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions.
Proceedings of the IEEE International Test Conference, 2021

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Micro-seismic source location determined by a modified objective function.
Eng. Comput., 2020

A novel method for locating the critical slip surface of a soil slope.
Eng. Appl. Artif. Intell., 2020

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.
CoRR, 2020

A new grey prediction model and its application to predicting landslide displacement.
Appl. Soft Comput., 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs.
Proceedings of the IEEE International Test Conference, 2020

Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level.
Proceedings of the IEEE European Test Symposium, 2020

Impact of Magnetic Coupling and Density on STT-MRAM Performance.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Device-Aware Test: A New Test Approach Towards DPPB Level.
Proceedings of the IEEE International Test Conference, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Electrical Modeling of STT-MRAM Defects.
Proceedings of the IEEE International Test Conference, 2018

2017
Gemini: A Novel Hardware and Software Implementation of High-performance PCIe SSD.
Int. J. Parallel Program., 2017

2015
Dysource: a high performance and scalable NAND flash controller architecture based on source synchronous interface.
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015


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