Sied Mehdi Fakhraie

Affiliations:
  • University of Tehran, Iran


According to our database1, Sied Mehdi Fakhraie authored at least 98 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
New Approximate Multiplier for Low Power Digital Signal Processing.
CoRR, 2020

2018
Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications.
Integr., 2018

A 256kb 9T Near-Threshold SRAM With 1k Cells per Bit-Line and Enhanced Write and Read Operations.
CoRR, 2018

Soft Realization: a Bio-inspired Implementation Paradigm.
CoRR, 2018

2017
Efficient utilization of imprecise computational blocks for hardware implementation of imprecision tolerant applications.
Microelectron. J., 2017

2016
Multiplierless filter-bank based multicarrier system by using canonical signed digit representation.
Wirel. Commun. Mob. Comput., 2016

Ultralow-Energy Variation-Aware Design: Adder Architecture Study.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Reliability aware throughput management of chip multi-processor architecture via thread migration.
J. Supercomput., 2016

A Novel Integer-Bit Estimation Scheme in Digital Filters Based on Probabilistic Behavior of Signals in the Internal Nodes.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor.
Microprocess. Microsystems, 2016

2015
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation.
IET Comput. Digit. Tech., 2015

Approximate Arithmetic for Low-Power Image Median Filtering.
Circuits Syst. Signal Process., 2015

Process variation-aware approximation for efficient timing management of digital circuits.
Proceedings of the 2015 IEEE East-West Design & Test Symposium, 2015

2014
Customized pipeline and instruction set architecture for embedded processing engines.
J. Supercomput., 2014

An analytical method for reliability aware instruction set extension.
J. Supercomput., 2014

Out-of-band power reduction by using computationally efficient cancellation pulses.
Phys. Commun., 2014

Implementation-aware selection of the custom instruction set for extensible processors.
Microprocess. Microsystems, 2014

Algorithm and FPGA implementation of interpolation-based soft output mmse mimo detector for 3GPP LTE.
IET Commun., 2014

2013
Defuzzification block: New algorithms, and efficient hardware and software implementation issues.
Eng. Appl. Artif. Intell., 2013

Coding techniques to mitigate out-of-band radiation in high data rate OFDM-based cognitive radios.
Comput. Electr. Eng., 2013

FPGA implementation of genetic algorithm for dynamic filter-bank-based multicarrier systems.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Reliability-aware cross-layer custom instruction screening.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012
Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors.
IEEE Trans. Neural Networks Learn. Syst., 2012

Adaptive fault-tolerant DVFS with dynamic online AVF prediction.
Microelectron. Reliab., 2012

Instruction set architectural guidelines for embedded packet-processing engines.
J. Syst. Archit., 2012

Deep out-of-band radiation reduction by using joint filterbank and cancellation carriers in cognitive radios.
Proceedings of the 6th International Symposium on Telecommunications, 2012

Vulnerability Analysis for Custom Instructions.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

CIVA: Custom instruction vulnerability analysis framework.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs.
IEEE Trans. Very Large Scale Integr. Syst., 2011

An accurate model for soft error rate estimation considering dynamic voltage and frequency scaling effects.
Microelectron. Reliab., 2011

Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling.
Microelectron. J., 2011

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling.
IET Comput. Digit. Tech., 2010

Parallel scalable hardware implementation of asynchronous discrete particle swarm optimization.
Eng. Appl. Artif. Intell., 2010

Parallel merged multiplier-accumulator coprocessor optimized for digital filters.
Comput. Electr. Eng., 2010

Energy-aware design space exploration of registerfile for extensible processors.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

All photonic analogue to digital and digital to analogue conversion techniques for digital radio over fibre system applications.
Proceedings of the 2010 ITU-Kaleidoscope: Beyond the Internet?, 2010

Reliability-Aware Dynamic Voltage and Frequency Scaling.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Instruction reliability analysis for embedded processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Sudoku Bit Arrangement for Combined Demosaicking and Watermarking in Digital Camera.
Proceedings of the Second International Conference on Advances in Databases, 2010

2009
Quantitative analysis of packet-processing applications regarding architectural guidelines for network-processing-engine development.
J. Syst. Archit., 2009

A cost-error tunable round-off method: Finite-length absorption.
IEICE Electron. Express, 2009

Computationally efficient active rule detection method: Algorithm and architecture.
Fuzzy Sets Syst., 2009

A New Approach for Combined Demosaicking and Watermarking in Digital Camera Pipeline.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

2008
Designing an ultra-high-speed multiply-accumulate structure.
Microelectron. J., 2008

A 65nm 10GHz pipelined MAC structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence.
Proceedings of the Design, Automation and Test in Europe, 2008

An Efficient and Extendable Modeling Approach for VLIW DSP Processors.
Proceedings of the Advances in Computer Science and Engineering, 2008

Design of a Custom Packet Switching Engine for Network Applications.
Proceedings of the Advances in Computer Science and Engineering, 2008

2007
An optimal structure for implementation of digital filters.
IEICE Electron. Express, 2007

15GHz low-voltage-swing carry-lookahead adder.
IEICE Electron. Express, 2007

A New Search Space Reduction Technique for Acquisition of UWB Signals in Multipath Channels.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications.
Proceedings of the 15th International Symposium on Modeling, 2007

Tertiary-Tree 12-GHz 32-bit Adder in 65nm Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Simulation of Voice Processing Applications through VLIW DSP Architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

SOPC-Based Architecture for Discrete Particle Swarm Optimization.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

HW/SW partitioning using discrete particle swarm.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
A 16-Bit Barrel-Shifter Implemented in Data-Driven Dynamic Logic ( D <sup>3</sup> L ).
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Minimizing the adder cost in multiple constant multipliers.
IEICE Electron. Express, 2006

Reconfigurable Parallel Hardware for Computing Local Linear Neuro-Fuzzy Model.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Evolutionary Multiprocessor Task Scheduling.
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Hardware implementation and comparison of new defuzzification techniques in fuzzy processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implementation of a high-speed low-power 32-bit adder in 70nm technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Neural network stream processing core (NnSP) for embedded systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Implementation of Multiplier Block with Reduced Adder Cost.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Dynamic voltage and frequency management based on variable update intervals for frequency setting.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Software Implementation Issues of Existing and New Defuzzification Methods.
Proceedings of the IEEE International Conference on Fuzzy Systems, 2006

SOPC-Based Parallel Genetic Algorithm.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

A Representation for Genetic-Algorithm-Based Multiprocessor Task Scheduling.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Experimental Evaluation of Different Realizations of Recursive CIC Filters.
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

Rapid Acquisition of Ultra-Wideband Signals in Multipath Environments.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Novel Neural Network GA-Optimized Controller for QoS Support in Wireless MACs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A High-Speed Low-Complexity VLSI SISO Architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Digital Audio Broadcasting System Modeling and Hardware Implementation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Digital Network Echo Cancellation Using Genetic Algorithm and Combined GA-LMS Method.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Genetic-algorithm Memory Minimisation for Designing Reconfigurable Ip Address Lookup Engine.
Int. J. Comput. Intell. Appl., 2005

Design and implementation of a fully digital 4FSK demodulator.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Cost-Performance Co-Analysis in VLSI Implementation of Existing and New Defuzzification Methods.
Proceedings of the 2005 International Conference on Computational Intelligence for Modelling Control and Automation (CIMCA 2005), 2005

2004
Scalable closed-boundary analog neural networks.
IEEE Trans. Neural Networks, 2004

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.
J. Electron. Test., 2004

A New Approach for Training of Artificial Neural Networks using Population Based Incremental Learning (PBIL).
Proceedings of the International Conference on Computational Intelligence, 2004

2003
Systematic test program generation for SoC testing using embedded processor.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

eUTDSP: a design study of a new VLIW-based DSP architecture.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Semi-coherent GFSK receiver for DECT standard.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A 68MHz multi-channel all-digital programmable oscillator.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D<sup>3</sup>L (D<sup>4</sup>L) logic styles.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An efficient BIST method for testing of embedded SRAMs.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
Low-power data-driven dynamic logic (D<sup>3</sup>L) [CMOS devices].
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A rail-to-rail, constant-G<sub>m</sub>, 1-volt CMOS opamp.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems.
Proceedings of the IEEE International Conference on Acoustics, 2000


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