Pasquale Cocchini

According to our database1, Pasquale Cocchini authored at least 13 papers between 1997 and 2023.

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Bibliography

2023
Towards A Correct-by-Construction FHE Model.
IACR Cryptol. ePrint Arch., 2023

An Automated Verification Framework for HalideIR-Based Compiler Transformations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

An Equivalence Checking Framework for Agile Hardware Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Accelerator design with decoupled hardware customizations: benefits and challenges: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration.
CoRR, 2021

RHNAS: Realizable Hardware and Neural Architecture Search.
CoRR, 2021

2004
Repeater scaling and its impact on CAD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003
A methodology for optimal repeater insertion in pipelined interconnects.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 International Symposium on Physical Design, 2003

2002
Concurrent flip-flop and repeater insertion for high performance integrated circuits.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2000
Fanout optimization using bipolar LT-trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

1998
Fanout optimization under a submicron transistor-level delay model.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
A comprehensive submicrometer MOST delay model and its application to CMOS buffers.
IEEE J. Solid State Circuits, 1997


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