Ginés Doménech-Asensi

Orcid: 0000-0002-2419-9275

Affiliations:
  • Universidad Politecnica de Cartagena, Spain


According to our database1, Ginés Doménech-Asensi authored at least 39 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
On the Use of Bayesian Networks for Real-Time Urban Traffic Measurements: a Case Study with Low-Cost Devices.
J. Signal Process. Syst., 2022

2021
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC.
Circuits Syst. Signal Process., 2021

A library-based tool to translate high level DNN models into hierarchical VHDL descriptions.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

2020
All-hardware SIFT implementation for real-time VGA images feature extraction.
J. Real Time Image Process., 2020

Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Simulation Acceleration of Image Filtering on CMOS Vision Chips Using Many-Core Processors.
Proceedings of the 2019 Forum for Specification and Design Languages, 2019

2018
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm.
Int. J. Circuit Theory Appl., 2018

FPGA real time synthesis of simplified SIFT algorithm.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

Traffic Metrics at Urban Intersections using a Low-Cost Image Processing Approach.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision.
Proceedings of the 12th International Conference on Distributed Smart Cameras, 2018

2017
Generation of new power processing structures exploiting genetic programming.
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Proactive Intelligent System for Optimizing Traffic Signaling.
Proceedings of the 2016 IEEE 14th Intl Conf on Dependable, 2016

2015
Distance Measurement Error in Time-of-Flight Sensors Due to Shot Noise.
Sensors, 2015

2014
Ambient assisted living system with capacitive occupancy sensor.
Expert Syst. J. Knowl. Eng., 2014

Simplification and hardware implementation of the feature descriptor vector calculation in the SIFT algorithm.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels.
Int. J. Circuit Theory Appl., 2013

An energy efficient middleware for an ad-hoc AAL wireless sensor network.
Ad Hoc Networks, 2013

Voltage boosters for on-chip solar cells on focal-plane processors.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
A system for ubiquitous fall monitoring at home via a wireless sensor network and a wearable mote.
Expert Syst. Appl., 2012

A fourth order CMOS band pass filter for PIR sensors.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
A secure energy-efficient m-banking application for mobile devices.
J. Syst. Softw., 2011

2010
Fuzzy logic technique for accurate analog circuits macromodel sizing.
Int. J. Circuit Theory Appl., 2010

2009
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Accurate and reusable macromodeling technique using a fuzzy-logic approach.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A behavioral model development methodology for microwave components and integration in VHDL-AMS.
Microelectron. J., 2007

Improvement of ANNs Performance to Generate Fitting Surfaces for Analog CMOS Circuits.
Proceedings of the Nature Inspired Problem-Solving Methods in Knowledge Engineering, 2007

Multiple adaptive neuro-fuzzy inference systems for accurate microwave CAD applications.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Description and Simulation of Bio-inspired Systems Using VHDL-AMS.
Proceedings of the Artificial Intelligence and Knowledge Engineering Applications: A Bioinspired Approach: First International Work-Conference on the Interplay Between Natural and Artificial Computation, 2005

Empirical Model Optimization of Microwave Devices Exploiting Genetic Algorithms.
Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

Empirical Model Generations of Microwave Devices Exploiting Linear Regression Models.
Proceedings of the 10th IEEE Symposium on Computers and Communications (ISCC 2005), 2005

2003
Current Mode CMOS Synthesis of a Motor-Control Neural System.
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

2002
Automated high level synthesis of hardware building blocks present in ART-based neural networks, from VHDL-AMS descriptions.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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