Giulio Galderisi
Orcid: 0000-0002-6997-5370
According to our database1,
Giulio Galderisi
authored at least 9 papers
between 2022 and 2025.
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Bibliography
2025
Bi-Linearity of Back Gated Schottky Barrier Transistors on an Industrial 22nm FDSOI Platform for Efficient In-Hardware Matrix-Vector Multiplication and Addition.
Proceedings of the 23rd IEEE Interregional NEWCAS Conference, 2025
Verilog-A Look-Up Table Model of a TIG-RFET Compatible with 22 nm FDSOI Design Rules Satisfying Gummel Symmetry.
Proceedings of the 14th International Conference on Modern Circuits and Systems Technologies, 2025
Electrostatically Adaptable Current Mirror based on Germanium Field-Effect Transistors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
Multi-Partner Project: Smart Sensor Analog Front-Ends Powered by Emerging Reconfigurable Devices (SENSOTERIC).
Proceedings of the Design, Automation & Test in Europe Conference, 2025
2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Special Session: Mitigating Side-Channel Attacks Through Circuit to Application Layer Approaches.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023
2022
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates.
IEEE Embed. Syst. Lett., 2022
Robust Reconfigurable Field Effect Transistors Process Route Enabling Multi-VT Devices Fabrication for Hardware Security Applications.
Proceedings of the Device Research Conference, 2022