Oskar Baumgartner

According to our database, Oskar Baumgartner authored at least 7 papers between 2018 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Study of the Variability and Design Considerations of Ferroelectric VNAND Memories With Polycrystalline Films Using An Experimentally Validated TCAD Model.

M. Thesberg, Franz Schanovsky, Zlatan Stanojevic, Oskar Baumgartner, Markus Karner

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

Analysis of an Inverter Logic Cell based on 3D Vertical NanoWire Junction-Less Transistors.

Lucas Réveil, Chhandak Mukherjee, Cristell Maneux, Marina Deng, François Marc, Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu, Arnaud Poittevin, Ian O'Connor, Oskar Baumgartner, David Pirker

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Co-integration Process Compatible Input/Output (I/O) Device Options for GAA Nanosheet Technology.

Gautam Gaddemane, Krishna K. Bhuwalka, Philippe Matagne, Gerhard Rzepa, Maarten L. Van De Put, Sybren Santermans, Oskar Baumgartner, Hao Wu, Geert Hellings

Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.

Gerhard Rzepa, Markus Karner, Oskar Baumgartner, Georg Strof, Franz Schanovsky, Ferdinand Mitterbauer, Christian Kernstock, Hui-Wen Karner, Pieter Weckx, Geert Hellings, Dieter Claes, Zhicheng Wu, Yang Xiang, Thomas Chiarella, Bertrand Parvais, Jérôme Mitard, Jacopo Franco, Ben Kaczer, Dimitri Linten, Zlatan Stanojevic

Proceedings of the IEEE International Reliability Physics Symposium, 2021

A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.

Franz Schanovsky, Devin Verreck, Antonio Arreghini, Gerhard Rzepa, Zlatan Stanojevic, Christian Kernstock, Oskar Baumgartner, Maarten Rosmeulen, Markus Karner

Proceedings of the IEEE International Memory Workshop, 2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka

Proceedings of the IEEE International Memory Workshop, 2021

2018

Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells.

Zlatan Stanojevic, Georg Strof, Franz Schanovsky, Klaus Steiner, Oskar Baumgartner, Christian Kernstock, Markus Karner

Proceedings of the 48th European Solid-State Device Research Conference, 2018