Shubham Rai

Alessandro Tempia Calvino

Heinz Riener

Giovanni De Micheli

Sai Manoj Pudukotai Dinakarrao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Formal Analysis of Camouflaged Reconfigurable Circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Reconfigurable FET Approximate Computing-based Accelerator for Deep Learning Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Discerning Limitations of GNN-based Attacks on Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Efficient Privacy-Aware Federated Learning by Elimination of Downstream Redundancy.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture.

[BibT_eX]

[DOI]

Johann Knechtel

Ozgur Sinanoglu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Securing Hardware through Reconfigurable Nano-Structures.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

Improving Technology Mapping for And-Inverter-Cones.

[BibT_eX]

[DOI]

Martin Thümmler

Alessandro Tempia Calvino

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

A Versatile Mapping Approach for Technology Mapping and Graph Optimization.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture".

[BibT_eX]

[DOI]

Gopal Raut

IEEE Open J. Circuits Syst., 2021

RECON: Resource-Efficient CORDIC-Based Neuron Architecture.

[BibT_eX]

[DOI]

Gopal Raut

IEEE Open J. Circuits Syst., 2021

A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies.

[BibT_eX]

[DOI]

Pallab Nath

Ansh Rupani

IEEE Access, 2021

END-TRUE: Emerging Nanotechnology-Based Double-Throughput True Random Number Generator.

[BibT_eX]

[DOI]

Nishant Gupta

Abhiroop Bhattacharjee

Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

Metastability with Emerging Reconfigurable Transistors: Exploiting Ambipolarity for Throughput.

[BibT_eX]

[DOI]

Abhiroop Bhattacharjee

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

RL-Guided Runtime-Constrained Heuristic Exploration for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Exploring Physical Synthesis for Circuits based on Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.

[BibT_eX]

[DOI]

Mengyun Liu

Anteneh Gebregiorgis

Debjyoti Bhattacharjee

Krishnendu Chakrabarty

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

A CORDIC Based Configurable Activation Function for ANN Applications.

[BibT_eX]

[DOI]

Gopal Raut

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

Exploiting Emerging Reconfigurable Technologies for Secure Devices.

[BibT_eX]

[DOI]

Ansh Rupani

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Emerging reconfigurable nanotechnologies: can they support future electronics?

[BibT_eX]

[DOI]

Srivatsa Rangachar Srinivasa

Patsy Cadareanu

Xunzhao Yin

Xiaobo Sharon Hu

Pierre-Emmanuel Gaillardon

Vijaykrishnan Narayanan

Proceedings of the International Conference on Computer-Aided Design, 2018

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Technology mapping flow for emerging reconfigurable silicon nanowire transistors.

[BibT_eX]

[DOI]

Michael Raitza