Giuseppe Di Cataldo

According to our database1, Giuseppe Di Cataldo authored at least 21 papers between 1993 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
CMOS Non-tailed differential pair.
Int. J. Circuit Theory Appl., 2016

2015
Single-miller all-passive compensation network for three-stage OTAs.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
High-performance frequency compensation topology for four-stage OTAs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2007
Two CMOS Current Feedback Operational Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

Mixed Full Adder topologies for high-performance low-power arithmetic circuits.
Microelectron. J., 2007

Miller Compensation: Optimization with Current Buffer/Amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A generalization of Miller formulae for nonlinear feedback networks.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

CMOS voltage feedback current amplifier.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

2006
High-speed CMOS unity-gain current amplifier.
Microelectron. J., 2006

Modeling of Feedback Analog Circuits with VHDL.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

RC-Chain: a Simple Model of Delay with a Ramp Input.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
CMOS interface for differential capacitive transducers.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

2002
Design guidelines for bipolar frequency dividers.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001
CML ring oscillators: oscillation frequency.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
High-speed voltage buffers for the experimental characterization of CMOS transconductance operational amplifiers.
IEEE Trans. Instrum. Meas., 1999

1996
Area-efficient design of three- and four-stage voltage multipliers for power integrated circuits.
Int. J. Circuit Theory Appl., 1996

1995
A CMOS CCII+.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Improved dynamic model of double and triple charge pumps to take current leakage into account.
Int. J. Circuit Theory Appl., 1994

Double and triple charge pumps with mos diodes: Dynamic models to an optimized design.
Int. J. Circuit Theory Appl., 1994

Optimized Design of 4 Stage Dickson Voltage Multiplier.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
New CMOS current mirrors with improved high-frequency response.
Int. J. Circuit Theory Appl., 1993


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