Gustavo H. Smaniotto

According to our database, Gustavo H. Smaniotto authored at least 9 papers between 2016 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Libra: An Automatic Design Methodology for CMOS Complex Gates.

Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Area-Aware Design of Static CMOS Complex Gates.

Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017

Transistor placement strategies for non-series-parallel cells.

Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Post-processing of supergate networks aiming cell layout optimization.

Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A post-processing methodology to improve the automatic design of CMOS gates at layout-level.

Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

A parallel Motion Estimation solution for heterogeneous System on Chip.

Mateus Melo, Gustavo H. Smaniotto, Henrique Maich, Luciano Volcan Agostini, Bruno Zatt, Leomar Rosa, Marcelo Schiavon Porto

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.

Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Physical design of supergate cells aiming geometrical optimizations.

Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.

Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016