Felipe S. Marques

Orcid: 0000-0003-1318-9992

Affiliations:
  • University of Pelotas, Technology Development Center, Brazil
  • Federal University of Pelotas, Group ofArchitectures and Integrated Circuits, GACI, Brazil
  • Nangate Inc


According to our database1, Felipe S. Marques authored at least 40 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Migortho: A Design Automation Flow for QCA Circuits.
IEEE Des. Test, 2022

2021
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.
ACM Trans. Design Autom. Electr. Syst., 2021

2020
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Straightforward Methodology for QCA Circuits Design.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Libra: An Automatic Design Methodology for CMOS Complex Gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Area-Aware Design of Static CMOS Complex Gates.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A Novel Sizing Method Aiming Security Against Differential Power Analysis.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Transistor Count Optimization in IG FinFET Network Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Transistor placement strategies for non-series-parallel cells.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Simulated Annealing Applied to LUT-Based FPGA Technology Mapping.
Proceedings of the Sixteenth Mexican International Conference on Artificial Intelligence, 2017

Post-processing of supergate networks aiming cell layout optimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A survey of path search algorithms for VLSI detailed routing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Graph-Based Transistor Network Generation Method for Supergate Design.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Physical design of supergate cells aiming geometrical optimizations.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Topological characteristics of logic networks generated by a graph-based methodology.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
Evaluating Geometric Aspects of Non-Series-Parallel Cells.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

2014
Exploring Independent Gates in FinFET-Based Transistor Network Generation.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A new general purpose line probe routing algorithm.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Improving the methodology to build non-series-parallel transistor arrangements.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Transistor-level optimization of CMOS complex gates.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Efficient transistor-level design of CMOS gates.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2010
Improvements on the detection of false paths by using unateness and satisfiability.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

SwitchCraft: a framework for transistor network design.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

KL-Cuts: A new approach for logic synthesis targeting multiple output blocks.
Proceedings of the Design, Automation and Test in Europe, 2010

2008
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007
A comparative study of CMOS gates with minimum transistor stacks.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

DAG based library-free technology mapping.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Fast disjoint transistor networks from BDDs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

2005
A new approach to the use of satisfiability in false path detection.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2002
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Testability Properties of BDDs.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002


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