Guy Cathébras

According to our database1, Guy Cathébras
  • authored at least 21 papers between 2001 and 2017.
  • has a "Dijkstra number"2 of four.



In proceedings 
PhD thesis 




Formal analysis of high-performance stabilized active-input current mirror.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Formal analysis of bandwidth enhancement for high-performance active-input current mirror.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

A phantom axon setup for validating models of action potential recordings.
Med. Biol. Engineering and Computing, 2016

In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A new shared-input amplifier architecture with enhanced noise-power efficiency for parallel biosignal recordings.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A Neural Stimulator Output Stage for Dodecapolar Electrodes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition.
Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Stream Manager, Easy CAD Tools Switching in Academic Context.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Hardware Implementation of Moment Functions in a CMOS Retina: Application to Pattern Recognition.
Proceedings of the Pattern Recognition and Image Analysis, Third Iberian Conference, 2007

A new method for implementing moment functions in a CMOS retina.
Mach. Vis. Appl., 2006

CMOS image sensor for spatiotemporal image acquisition.
J. Electronic Imaging, 2006

Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Hardware Computation of Moment Functions in a Silicon Retina using Binary Patterns.
Proceedings of the International Conference on Image Processing, 2006

Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

An Image Sensor with Global Motion Estimation for Micro Camera Module.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2005

Retina for pattern matching in standard 0.6-µm complementary metal oxide semiconductor technology.
J. Electronic Imaging, 2004

Integration of Robustness in the Design of a Cell.
Proceedings of the SOC Design Methodologies, 2001

A correlation retina for real-time pattern recognition.
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001