Serge Bernard
Orcid: 0000-0003-1772-0592
According to our database1,
Serge Bernard
authored at least 80 papers
between 2000 and 2023.
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Bibliography
2023
On the Use of the Indirect Test Strategy for Lifetime Performance Monitoring of RF Circuits.
J. Electron. Test., April, 2023
First Step Towards a Fully-Miniaturized Intra-body Communication Transceiver Based on Galvanic Coupling.
Proceedings of the Advances in Information and Communication, 2023
2022
Bioimpedance Spectroscopy Helps Monitor the Impact of Electrical Stimulation on Muscle Cells.
IEEE Access, 2022
2021
J. Electron. Test., 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
In vitro impedance spectroscopy: A MEA-based measurement bench for myoblasts cultures monitoring.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021
2020
Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits.
J. Electron. Test., 2020
Implementing indirect test of RF circuits without compromising test quality: a practical case study.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
2019
Breaking the speed-power-accuracy trade-off in current mirror with non-linear CCII feedback.
Microelectron. J., 2019
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
2018
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints.
J. Electron. Test., 2018
A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Wideband Fully Differential Current Driver with Optimized Output Impedance for Bioimpedance Measurements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 12th International Conference on Sensing Technology, 2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
Efficient Objective Metric Tool for Medical Electrical Device Development: Eye Phantom for Glaucoma Diagnosis Device.
J. Sensors, 2017
J. Electron. Test., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Formal analysis of bandwidth enhancement for high-performance active-input current mirror.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
2016
Medical Biol. Eng. Comput., 2016
2015
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.
Microelectron. J., 2015
Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015
In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Relevance of impedance spectroscopy for the monitoring of implant-induced fibrosis: A preliminary study.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
2014
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.
Microelectron. J., 2014
Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
New implementions of predictive alternate analog/RF test with augmented model redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.
Microelectron. J., 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Implementing model redundancy in predictive alternate test to improve test confidence.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Making predictive analog/RF alternate test strategy independent of training set size.
Proceedings of the 2012 IEEE International Test Conference, 2012
A new shared-input amplifier architecture with enhanced noise-power efficiency for parallel biosignal recordings.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter.
IEEE Trans. Instrum. Meas., 2011
J. Electron. Test., 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Sensitivity of a frequency-selective electrode based on spatial spectral properties of the extracellular AP of myelinated nerve fibers.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
VLSI Design, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the Biomedical Engineering Systems and Technologies, 2008
Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008
2007
IET Comput. Digit. Tech., 2007
Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 12th European Test Symposium, 2007
2006
J. Electron. Test., 2006
IEEE Des. Test Comput., 2006
Proceedings of the 11th European Test Symposium, 2006
2005
J. Electron. Test., 2005
2004
J. Electron. Test., 2004
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electron. Test., 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
2003
Microelectron. J., 2003
J. Electron. Test., 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2002
Estimating Static Parameters of A-to-D Converters from Spectral Analysis.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the 7th European Test Workshop, 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
2001
J. Electron. Test., 2001
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area.
Proceedings of the 2nd Latin American Test Workshop, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
Proceedings of the SOC Design Methodologies, 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the 5th European Test Workshop, 2000