Serge Bernard

According to our database1, Serge Bernard authored at least 73 papers between 2000 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


Online presence:



Evaluation of a Two-Tier Adaptive Indirect Test Flow for a Front-End RF Circuit.
J. Electron. Test., 2021

Exploring on-line RF performance monitoring based on the indirect test strategy.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

In vitro impedance spectroscopy: A MEA-based measurement bench for myoblasts cultures monitoring.
Proceedings of the XXXVI Conference on Design of Circuits and Integrated Systems, 2021

Investigations on the Use of Ensemble Methods for Specification-Oriented Indirect Test of RF Circuits.
J. Electron. Test., 2020

Implementing indirect test of RF circuits without compromising test quality: a practical case study.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICs.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Very Low Resource Digital Implementation of Bioimpedance Analysis.
Sensors, 2019

Breaking the speed-power-accuracy trade-off in current mirror with non-linear CCII feedback.
Microelectron. J., 2019

Which metrics to use for RF indirect test strategy?
Proceedings of the 16th International Conference on Synthesis, 2019

Use of ensemble methods for indirect test of RF circuits: can it bring benefits?
Proceedings of the IEEE Latin American Test Symposium, 2019

On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints.
J. Electron. Test., 2018

A Hybrid Bioimpedance Spectroscopy Architecture for a Wide Frequency Exploration of Tissue Electrical Properties.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Wideband Fully Differential Current Driver with Optimized Output Impedance for Bioimpedance Measurements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Multitone Analysis for Bioimpedance Spectroscopy using Minimal Digital Ressource.
Proceedings of the 12th International Conference on Sensing Technology, 2018

Improvement of Active-Input Current Mirrors Using Adaptive Biasing Technique.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

Efficient Objective Metric Tool for Medical Electrical Device Development: Eye Phantom for Glaucoma Diagnosis Device.
J. Sensors, 2017

New Calibration Technique of Contact-less Resonant Biosensor.
J. Electron. Test., 2017

Formal analysis of high-performance stabilized active-input current mirror.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Formal analysis of bandwidth enhancement for high-performance active-input current mirror.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

A phantom axon setup for validating models of action potential recordings.
Medical Biol. Eng. Comput., 2016

Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.
Microelectron. J., 2015

Exploring the limit of ENG spatio-temporal filtering for velocity-selectivity.
Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015

In-silico Phantom Axon: Emulation of an Action Potential Propagating Along Artificial Nerve Fiber.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Relevance of impedance spectroscopy for the monitoring of implant-induced fibrosis: A preliminary study.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Microelectron. J., 2014

Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.
Microelectron. J., 2014

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.
Proceedings of the 15th Latin American Test Workshop, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

New implementions of predictive alternate analog/RF test with augmented model redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.
Microelectron. J., 2013

Joint special Issue from best papers of DTIS'10 and DTIS'11.
Microelectron. J., 2013

Accurate and efficient analytical electrical model of antenna for NFC applications.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Implementing model redundancy in predictive alternate test to improve test confidence.
Proceedings of the 18th IEEE European Test Symposium, 2013

Smart selection of indirect parameters for DC-based alternate RF IC testing.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Making predictive analog/RF alternate test strategy independent of training set size.
Proceedings of the 2012 IEEE International Test Conference, 2012

A new shared-input amplifier architecture with enhanced noise-power efficiency for parallel biosignal recordings.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter.
IEEE Trans. Instrum. Meas., 2011

Digital Test Method for Embedded Converters with Unknown-Phase Harmonics.
J. Electron. Test., 2011

Fascicle-selective multi-contact cuff electrode.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Sensitivity of a frequency-selective electrode based on spatial spectral properties of the extracellular AP of myelinated nerve fibers.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

A multi-converter DFT technique for complex SIP: Concepts and validation.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator.
VLSI Design, 2008

Wireless Test Structure for Integrated Systems.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Neural Stimulator Output Stage for Dodecapolar Electrodes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition.
Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.
Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC.
IET Comput. Digit. Tech., 2007

Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 12th European Test Symposium, 2007

System-in-Package, a Combination of Challenges and Solutions.
Proceedings of the 12th European Test Symposium, 2007

A First Step for an INL Spectral-Based BIST: The Memory Optimization.
J. Electron. Test., 2006

A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Des. Test Comput., 2006

A Low Cost Alternative Method for Harmonics Estimation in a BIST Context.
Proceedings of the 11th European Test Symposium, 2006

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electron. Test., 2005

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
J. Electron. Test., 2004

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electron. Test., 2004

A-to-D converters static error detection from dynamic parameter measurement.
Microelectron. J., 2003

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.
J. Electron. Test., 2003

A New Methodology For ADC Test Flow Optimization.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A high accuracy triangle-wave signal generator for on-chip ADC testing.
Proceedings of the 7th European Test Workshop, 2002

European Network for Test Education.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.
J. Electron. Test., 2001

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.
J. Electron. Test., 2001

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Boolean and current detection of MOS transistor with gate oxide short.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
Proceedings of the SOC Design Methodologies, 2001

Analog BIST Generator for ADC Testing.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Implementation of a linear histogram BIST for ADCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Hardware Resource Minimization for Histogram-Based ADC BIST.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Towards an ADC BIST scheme using the histogram test technique.
Proceedings of the 5th European Test Workshop, 2000