Vincent Kerzerho

According to our database1, Vincent Kerzerho authored at least 27 papers between 2006 and 2018.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
On-chip Generation of Sine-wave Summing Digital Signals: an Analytic Study Considering Implementation Constraints.
J. Electronic Testing, 2018

Wideband Fully Differential Current Driver with Optimized Output Impedance for Bioimpedance Measurements.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Efficient Objective Metric Tool for Medical Electrical Device Development: Eye Phantom for Glaucoma Diagnosis Device.
J. Sensors, 2017

New Calibration Technique of Contact-less Resonant Biosensor.
J. Electronic Testing, 2017

Formal analysis of high-performance stabilized active-input current mirror.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Formal analysis of bandwidth enhancement for high-performance active-input current mirror.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2015
Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies.
Microelectronics Journal, 2015

A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Toward Adaptation of ADCs to Operating Conditions through On-chip Correction.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2014
Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements.
Microelectronics Journal, 2014

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing.
Proceedings of the 15th Latin American Test Workshop, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

New implementions of predictive alternate analog/RF test with augmented model redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC.
Microelectronics Journal, 2013

Accurate and efficient analytical electrical model of antenna for NFC applications.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Implementing model redundancy in predictive alternate test to improve test confidence.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Smart selection of indirect parameters for DC-based alternate RF IC testing.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Making predictive analog/RF alternate test strategy independent of training set size.
Proceedings of the 2012 IEEE International Test Conference, 2012

2011
Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter.
IEEE Trans. Instrumentation and Measurement, 2011

Digital Test Method for Embedded Converters with Unknown-Phase Harmonics.
J. Electronic Testing, 2011

2010
Predicting dynamic specifications of ADCs with a low-quality digital input signal.
Proceedings of the 15th European Test Symposium, 2010

2008
ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator.
VLSI Design, 2008

2007
Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC.
IET Computers & Digital Techniques, 2007

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 12th European Test Symposium, 2007

2006
A First Step for an INL Spectral-Based BIST: The Memory Optimization.
J. Electronic Testing, 2006

A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Design & Test of Computers, 2006

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
Proceedings of the 11th European Test Symposium, 2006


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