Yves Bertrand

According to our database, Yves Bertrand authored at least 89 papers between 1992 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

"Capacitive Sensor" to Measure Flow Electrification and Prevent Electrostatic Hazards.

Thierry Paillat, Gérard Touchard, Yves Bertrand

Sensors, 2012

2009

Remote Labs for Industrial IC Testing.

Beatrice Pradarelli, Laurent Latorre, Marie-Lise Flottes, Yves Bertrand, Pascal Nouet

IEEE Trans. Learn. Technol., 2009

Consistency constraints and 3D building reconstruction.

Sébastien Horna, Daniel Méneveaux, Guillaume Damiand, Yves Bertrand

Comput. Aided Des., 2009

An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions.

Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

2008

On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring.

Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Multipolar Electrode and Preamplifier Design for ENG-Signal Acquisition.

Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand

Proceedings of the Biomedical Engineering Systems and Technologies, 2008

Considerations on Improving the Design of CUFF Electrode for ENG Recording - Geometrical Approach, Dedicated IC, Sensitivity, Noise Rejection.

Fabien Soulier, Lionel Gouyet, Guy Cathébras, Serge Bernard, David Guiraud, Yves Bertrand

Proceedings of the First International Conference on Biomedical Electronics and Devices, 2008

2007

Low-noise ASIC and New Layout of Multipolar Electrode for both High ENG Selectivity and Parasitic Signal Rejection.

Serge Bernard, Lionel Gouyet, Guy Cathébras, Fabien Soulier, David Guiraud, Yves Bertrand

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Building 3D indoor scenes topology from 2D architectural plans.

Sébastien Horna, Guillaume Damiand, Daniel Méneveaux, Yves Bertrand

Proceedings of the GRAPP 2007, 2007

Generic computation of bulletin boards into geometric kernels.

Mehdi Baba-ali, David Marcheix, Xavier Skapin, Yves Bertrand

Proceedings of the 5th International Conference on Computer Graphics, 2007

2005

Connectivity compression in an arbitrary dimension.

Sylvain Prat, Patrick Gioia, Yves Bertrand, Daniel Méneveaux

Vis. Comput., 2005

Delay Testing Viability of Gate Oxide Short Defects.

Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand

J. Comput. Sci. Technol., 2005

Automatic Building of Structured Geological Models.

Sylvain Brandel, Sébastien Schneider, Michel Perrin, Nicolas Guiard, Jean-François Rainaud, Pascal Lienhardt, Yves Bertrand

J. Comput. Inf. Sci. Eng., 2005

Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

J. Electron. Test., 2005

Test Engineering Education in Europe - The CRTC experience through the EuNICE-Test project.

Laurent Latorre, Yves Bertrand, Michel Robert, Marie-Lise Flottes

Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

2004

Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.

Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell

J. Electron. Test., 2004

Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

J. Electron. Test., 2004

Topological model for two-dimensional image representation: definition and optimal extraction algorithm.

Guillaume Damiand, Yves Bertrand, Christophe Fiorio

Comput. Vis. Image Underst., 2004

New implantable stimulator for the FES of paralyzed muscles.

Jean-Denis Techer, Serge Bernard, Yves Bertrand, Guy Cathébras, David Guiraud

Proceedings of the 33rd European Solid-State Circuits Conference, 2004

Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.

Marie-Lise Flottes, Yves Bertrand, Luz Balado, Emili Lupon, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

A-to-D converters static error detection from dynamic parameter measurement.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell

Microelectron. J., 2003

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

J. Electron. Test., 2003

On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

J. Electron. Test., 2003

An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.

Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei

IEEE Des. Test Comput., 2003

Test Engineering Education in Europe: the EuNICE-Test Project.

Yves Bertrand, Marie-Lise Flottes, Luz Balado, Joan Figueras, Anton Biasizzo, Franc Novak, Stefano Di Carlo, Paolo Prinetto, Nicoleta Pricopi, Hans-Joachim Wunderlich, Jean-Pierre Van der Heyden

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A New Methodology For ADC Test Flow Optimization.

Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Delay Testing of MOS Transistor with Gate Oxide Short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Spécifications formelles du chanfreinage.

Franck Ledoux, Jean-Marc Mota, Agnès Arnould, Catherine Dubois, Pascale Le Gall, Yves Bertrand

Tech. Sci. Informatiques, 2002

Improving Defect Detection in Static-Voltage Testing.

Michel Renovell, Florence Azaïs, Yves Bertrand

IEEE Des. Test Comput., 2002

Evaluation of the Oscillation-based Test Methodology for Micro-Electro-Mechanical Systems.

Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Testing Resonant Micro-Electro-Mechanical Sensors using the Oscillation-based Test Methodology.

Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet

Proceedings of the 3rd Latin American Test Workshop, 2002

Estimating Static Parameters of A-to-D Converters from Spectral Analysis.

Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski

Proceedings of the 3rd Latin American Test Workshop, 2002

Modeling gate oxide short defects in CMOS minimum transistors.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 7th European Test Workshop, 2002

A high accuracy triangle-wave signal generator for on-chip ADC testing.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 7th European Test Workshop, 2002

European Network for Test Education.

Yves Bertrand, Marie-Lise Flottes, Florence Azaïs, Serge Bernard, Laurent Latorre, Regis Lorival

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

On the Use of an Oscillation-Based Test Methodology for CMOS Micro-Electro-Mechanical Systems.

Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet

Proceedings of the 2002 Design, 2002

2001

On the detectability of CMOS floating gate transistor faults.

André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Test and Testability of a Monolithic MEMS for Magnetic Field Sensing.

Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet

J. Electron. Test., 2001

Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

J. Electron. Test., 2001

A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

J. Electron. Test., 2001

N-Dimensional Gregory-Bezier for N-Dimensional Cellular Complexes.

Sylvain Thery, Dominique Bechmann, Yves Bertrand

Proceedings of the 9-th International Conference in Central Europe on Computer Graphics, 2001

Geometric Modelling with CASL.

Franck Ledoux, Agnès Arnould, Pascale Le Gall, Yves Bertrand

Proceedings of the Recent Trends in Algebraic Development Techniques, 2001

A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.

Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Electrical Analysis of Gate Oxide Short in MOS Technologies.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand

Proceedings of the 2nd Latin American Test Workshop, 2001

On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area.

Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell

Proceedings of the 2nd Latin American Test Workshop, 2001

Boolean and current detection of MOS transistor with gate oxide short.

Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Noise optimisation of a piezoresistive CMOS MEMS for magnetic field sensing.

Vincent Beroulle, Yves Bertrand, Laurent Latorre, Pascal Nouet

Proceedings of the SOC Design Methodologies, 2001

On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

Proceedings of the SOC Design Methodologies, 2001

Analog BIST Generator for ADC Testing.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Implementation of a linear histogram BIST for ADCs.

Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Topological 3D-manifolds: a statistical study of the cells.

Jean Françon, Yves Bertrand

Theor. Comput. Sci., 2000

Thickening: an operation for animation.

Sylvain Brandel, Dominique Bechmann, Yves Bertrand

Comput. Animat. Virtual Worlds, 2000

Combining Functional and Structural Approaches for Switched-Current Circuit Testing.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

J. Electron. Test., 2000

Hardware Resource Minimization for Histogram-Based ADC BIST.

Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

On the Temperature Dependencies of Analog BIST.

Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs

Proceedings of the 1st Latin American Test Workshop, 2000

Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters.

Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell

Proceedings of the 1st Latin American Test Workshop, 2000

Topological Encoding of 3D Segmented Images.

Yves Bertrand, Guillaume Damiand, Christophe Fiorio

Proceedings of the Discrete Geometry for Computer Imagery, 9th International Conference, 2000

Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.

Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski

Proceedings of the 2000 Design, 2000

TI-BIST: a temperature independent analog BIST for switched-capacitor filters.

Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Detection of Defects Using Fault Model Oriented Test Sequences.

Michel Renovell, Florence Azaïs, Yves Bertrand

J. Electron. Test., 1999

A Successful Distance-Learning Experience for IC Test Education.

Yves Bertrand, Florence Azaïs, Marie-Lise Flottes, Regis Lorival

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

Optimal conditions for Boolean and current detection of floating gate faults.

Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Functional and structural testing of switched-current circuits.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

Proceedings of the 4th European Test Workshop, 1999

Border Map: A Topological Representation for nD Image Analysis.

Yves Bertrand, Christophe Fiorio, Yann Pennaneach

Proceedings of the Discrete Geometry for Computer Imagery, 1999

Design, Characterization & Modelling of a CMOS Magnetic Field Sensor.

Laurent Latorre, Yves Bertrand, P. Hazard, Francis Pressecq, Pascal Nouet

Proceedings of the 1999 Design, 1999

1998

Design-For-Testability for Switched-Current Circuits.

Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing.

Michel Renovell, Salvador Mir, F. Azaïs M. Lubaszewsk, Yves Bertrand

Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

STIGMA: a 4-dimensional modeller for animation.

Sylvain Brandel, Dominique Bechmann, Yves Bertrand

Proceedings of the Eurographics Workshop on Computer Animation and Simulation 1998, Lisbon, Portugal, August 31, 1998

Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 1998 Design, 1998

BISTing Switched-Current Circuits.

Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.

Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Continuous free form deformation.

Dominique Bechmann, Yves Bertrand, Sylvain Thery

Comput. Networks ISDN Syst., 1997

Test Strategy Sensitivity to Defect Parameters.

Michel Renovell, Yves Bertrand

Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

On-chip analog output response compaction.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the European Design and Test Conference, 1997

MOSAIC: a multiple-strategy oriented sequential ATPG for integrated circuits.

A. Dargelas, C. Gauthron, Yves Bertrand

Proceedings of the European Design and Test Conference, 1997

1996

Bridging fault coverage improvement by power supply control.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

The multi-configuration: A DFT technique for analog circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the Dependable Computing, 1996

1995

The concept of resistance interval: a new parametric model for realistic resistive bridging fault.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Serial transistor network modeling for bridging fault simulation.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

A design-for-test technique for multistage analog circuits.

Michel Renovell, Florence Azaïs, Yves Bertrand

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Test configurations to enhance the testability of sequential circuits.

S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Algebraic Specification of a 3D-Modeler Based on Hypermaps.

Yves Bertrand, Jean-François Dufourd

CVGIP Graph. Model. Image Process., 1994

CMOS bridging fault modeling.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds.

Michel Renovell, P. Huc, Yves Bertrand

Proceedings of the Dependable Computing, 1994

1993

A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Sixth International Conference on VLSI Design, 1993

Algebraic Specification and Development in Geometric Modeling.

Yves Bertrand, Jean-François Dufourd, Jean Françon, Pascal Lienhardt

Proceedings of the TAPSOFT'93: Theory and Practice of Software Development, 1993

Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.

Yves Bertrand, Frédéric Bancel, Michel Renovell

Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1992

A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs.

Michel Renovell, M. Ildevert, Yves Bertrand

Proceedings of the Fifth International Conference on VLSI Design, 1992