Philippe Coussy

According to our database1, Philippe Coussy authored at least 87 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An Efficient and Flexible Stochastic CGRA Mapping Approach.
ACM Trans. Embed. Comput. Syst., 2023

2022
Energy Efficient Hardware Loop Based Optimization for CGRAs.
J. Signal Process. Syst., 2022

Generating Efficient FPGA-based CNN Accelerators from High-Level Descriptions.
J. Signal Process. Syst., 2022

Protecting Behavioral IPs During Design Time: Key-Based Obfuscation Techniques for HLS in the Cloud.
Behavioral Synthesis for Hardware Security, 2022

2021
Floating Point CGRA based Ultra-Low Power DSP Accelerator.
J. Signal Process. Syst., 2021

Exploration and Generation of Efficient FPGA-based Deep Neural Network Accelerators.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Hardware Based Loop Optimization for CGRA Architectures.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

Extended RISC-V hardware architecture for future digital communication systems.
Proceedings of the 4th IEEE 5G World Forum, 2021

2020
Deep Neural Networks Characterization Framework for Efficient Implementation on Embedded Systems.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Toward Secured IoT Devices: A Shuffled 8-Bit AES Hardware Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Energy Efficient Acceleration Of Floating Point Applications Onto CGRA.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Clone-Based Encoded Neural Networks to Design Efficient Associative Memories.
IEEE Trans. Neural Networks Learn. Syst., 2019

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Solving Memory Access Conflicts in LTE-4G Standard.
Proceedings of the IEEE International Conference on Acoustics, 2019

Context-memory Aware Mapping for Energy Efficient Acceleration with CGRAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Transient Key-based Obfuscation for HLS in an Untrusted Cloud Environment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A Heterogeneous Cluster with Reconfigurable Accelerator for Energy Efficient Near-Sensor Data Analytics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Efficient scalable hardware architecture for highly performant encoded neural networks.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

A 142MOPS/mW integrated programmable array accelerator for smart visual processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Efficient mapping of CDFG onto coarse-grained reconfigurable array architectures.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Scalable Design Approach to Efficiently Map Applications on CGRAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A dynamically reconfigurable ECC decoder architecture.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Associative Memory based on clustered Neural Networks: Improved model and architecture for Oriented Edge Detection.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Large-Scale Spiking Neural Networks using Neuromorphic Hardware Compatible Models.
ACM J. Emerg. Technol. Comput. Syst., 2015

Fully Binary Neural Network Model and Optimized Hardware Architectures for Associative Memories.
ACM J. Emerg. Technol. Comput. Syst., 2015

Improving storage of patterns in recurrent neural networks: Clone-based model and architecture.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Restricted Clustered Neural Network for Storing Real Data.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

In-place memory mapping approach for optimized parallel hardware interleaver architectures.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Embedding polynomial time memory mapping and routing algorithms on-chip to design configurable decoder architectures.
Proceedings of the IEEE International Conference on Acoustics, 2014

A memory mapping approach based on network customization to design conflict-free parallel hardware architectures.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

An automated design approach to map applications on CGRAs.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A design approach to automatically generate on-chip monitors during high-level synthesis of hardware accelerator.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

A HLS-Based Toolflow to Design Next-Generation Heterogeneous Many-Core Platforms with Shared Memory.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

A tightly-coupled hardware controller to improve scalability and programmability of shared-memory heterogeneous clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations.
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013
A First Step Toward On-Chip Memory Mapping for Parallel Turbo and LDPC Decoders: A Polynomial Time Mapping Algorithm.
IEEE Trans. Signal Process., 2013

Introduction de la prédiction de branchement dans la synthèse de haut niveau.
Tech. Sci. Informatiques, 2013

A conflict-free memory mapping approach to design parallel hardware interleaver architectures with optimized network and controller.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

On-chip implementation of memory mapping algorithm to support flexible decoder architecture.
Proceedings of the IEEE International Conference on Acoustics, 2013

A memory mapping approach for network and controller optimization in parallel interleaver architectures.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Dynamic branch prediction for high-level synthesis.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Architecture and programming model support for efficient heterogeneous computing on tigthly-coupled shared-memory clusters.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
ESL Design Methodology.
J. Electr. Comput. Eng., 2012

A Dedicated Approach to Explore Design Space for Hardware Architecture of Turbo Decoders.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

A design approach dedicated to network-based and conflict-free parallel interleavers.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

OpenMP-based Synergistic Parallelization and HW Acceleration for On-Chip Shared-Memory Clusters.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
An approach based on edge coloring of tripartite graph for designing parallel LDPC interleaver architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A methodology based on Transportation problem modeling for designing parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2011

High-Level Synthesis: On the path to ESL design.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
High-Level Synthesis for Designing Multimode Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Design Flow for Critical Embedded Systems.
Proceedings of the IEEE Fifth International Symposium on Industrial Embedded Systems, 2010

A memory mapping approach for parallel interleaver design with multiples read and write accesses.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of parallel LDPC interleaver architecture: A bipartite edge coloring approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Bitwidth-aware high-level synthesis for designing low-power DSP applications.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Static Address Generation Easing: a design methodology for parallel interleaver architectures.
Proceedings of the IEEE International Conference on Acoustics, 2010

Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

An introduction to the SystemC synthesis subset standard.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009
Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.
J. Signal Process. Syst., 2009

Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design.
IEEE Des. Test Comput., 2009

An Introduction to High-Level Synthesis.
IEEE Des. Test Comput., 2009

2008
Multiple Word-Length High-Level Synthesis.
EURASIP J. Embed. Syst., 2008

2007
Constrained algorithmic IP design for system-on-chip.
Integr., 2007

Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels
CoRR, 2007

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A design flow dedicated to multi-mode architectures for DSP applications.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A design methodology for space-time adapter.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Behavioral description model BDM for design space exploration: A case study of HIS algorithm for MC-CDMA system.
Proceedings of the 15th European Signal Processing Conference, 2007

Application of a design space exploration tool to enhance interleaver generation.
Proceedings of the 15th European Signal Processing Conference, 2007

Synthesis of Multimode digital signal processing systems.
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007

2006
A formal method for hardware IP design and integration under I/O and timing constraints.
ACM Trans. Embed. Comput. Syst., 2006

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI
CoRR, 2006

Design Space Exploration of DSP Applications Based on Behavioral Description Models.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

2005
High-level synthesis under I/O timing and memory constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A more efficient and flexible DSP design flow from Matlab-Simulink [FFT algorithm example].
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

SystemCmantic: A high level Modelling and Co-Design Framework.
Proceedings of the Forum on specification and Design Languages, 2005

2004
A methodology for IP integration into DSP SoC: a case study of a MAP algorithm for turbo decoder.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

2003
Communication and Timing Constraints Analysis for IP Design and Integration.
Proceedings of the IFIP VLSI-SoC 2003, 2003

2002
A design methodology for IP integration.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

IP cores integration in DSP System-on-chip designs.
Proceedings of the 11th European Signal Processing Conference, 2002

A design methodology for integrating IP into SOC systems.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002


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