Abhishek A. Sinkar
According to our database1,
Abhishek A. Sinkar
authored at least 18 papers
between 2009 and 2016.
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Bibliography
2016
VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency.
Proceedings of the 53rd Annual Design Automation Conference, 2016
2014
Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Quantitative comparison of the power reduction techniques for samsung reconfigurable processor.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Improving platform energy: chip area trade-off in near-threshold computing environment.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013
2012
Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Workload-aware voltage regulator optimization for power efficient multi-core processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Cost-effective power delivery to support per-core voltage domains for power-constrained processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Statistical static timing analysis considering leakage variability in power gated designs.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009